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[PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction
From: |
Siarhei Volkau |
Subject: |
[PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction |
Date: |
Thu, 8 Jun 2023 13:42:19 +0300 |
The instruction is used to determine sign of four 16-bit
packed data in parallel.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
target/mips/tcg/mxu_translate.c | 85 +++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index dc985342d6..7970b70fe1 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -407,6 +407,7 @@ enum {
OPC_MXU__POOL19 = 0x38,
OPC_MXU__POOL20 = 0x39,
OPC_MXU__POOL21 = 0x3A,
+ OPC_MXU_Q16SCOP = 0x3B,
};
@@ -3541,6 +3542,7 @@ static void gen_mxu_d32asum(DisasContext *ctx)
* S32EXTR S32LUI
* S32EXTRV
* Q16SAT
+ * Q16SCOP
*/
/*
@@ -3808,6 +3810,86 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)
}
}
+/*
+ * Q16SCOP XRa, XRd, XRb, XRc
+ * Determine sign of quad packed 16-bit signed values
+ * in XRb and XRc put result in XRa and XRd respectively.
+ */
+static void gen_mxu_q16scop(DisasContext *ctx)
+{
+ uint32_t XRd, XRc, XRb, XRa;
+
+ XRd = extract32(ctx->opcode, 18, 4);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+ TCGv t4 = tcg_temp_new();
+
+ TCGLabel *l_b_hi_lt = gen_new_label();
+ TCGLabel *l_b_hi_gt = gen_new_label();
+ TCGLabel *l_b_lo = gen_new_label();
+ TCGLabel *l_b_lo_lt = gen_new_label();
+ TCGLabel *l_c_hi = gen_new_label();
+ TCGLabel *l_c_hi_lt = gen_new_label();
+ TCGLabel *l_c_hi_gt = gen_new_label();
+ TCGLabel *l_c_lo = gen_new_label();
+ TCGLabel *l_c_lo_lt = gen_new_label();
+ TCGLabel *l_done = gen_new_label();
+
+ gen_load_mxu_gpr(t0, XRb);
+ gen_load_mxu_gpr(t1, XRc);
+
+ tcg_gen_sextract_tl(t2, t0, 16, 16);
+ tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_hi_lt);
+ tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_b_hi_gt);
+ tcg_gen_movi_tl(t3, 0);
+ tcg_gen_br(l_b_lo);
+ gen_set_label(l_b_hi_lt);
+ tcg_gen_movi_tl(t3, 0xffff0000);
+ tcg_gen_br(l_b_lo);
+ gen_set_label(l_b_hi_gt);
+ tcg_gen_movi_tl(t3, 0x00010000);
+
+ gen_set_label(l_b_lo);
+ tcg_gen_sextract_tl(t2, t0, 0, 16);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_c_hi);
+ tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_lo_lt);
+ tcg_gen_ori_tl(t3, t3, 0x00000001);
+ tcg_gen_br(l_c_hi);
+ gen_set_label(l_b_lo_lt);
+ tcg_gen_ori_tl(t3, t3, 0x0000ffff);
+ tcg_gen_br(l_c_hi);
+
+ gen_set_label(l_c_hi);
+ tcg_gen_sextract_tl(t2, t1, 16, 16);
+ tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_c_hi_lt);
+ tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_c_hi_gt);
+ tcg_gen_movi_tl(t4, 0);
+ tcg_gen_br(l_c_lo);
+ gen_set_label(l_c_hi_lt);
+ tcg_gen_movi_tl(t4, 0xffff0000);
+ tcg_gen_br(l_c_lo);
+ gen_set_label(l_c_hi_gt);
+ tcg_gen_movi_tl(t4, 0x00010000);
+
+ gen_set_label(l_c_lo);
+ tcg_gen_sextract_tl(t2, t1, 0, 16);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_done);
+ tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_c_lo_lt);
+ tcg_gen_ori_tl(t4, t4, 0x00000001);
+ tcg_gen_br(l_done);
+ gen_set_label(l_c_lo_lt);
+ tcg_gen_ori_tl(t4, t4, 0x0000ffff);
+
+ gen_set_label(l_done);
+ gen_store_mxu_gpr(t3, XRa);
+ gen_store_mxu_gpr(t4, XRd);
+}
/*
* MXU instruction category: align
@@ -4801,6 +4883,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
case OPC_MXU__POOL21:
decode_opc_mxu__pool21(ctx);
break;
+ case OPC_MXU_Q16SCOP:
+ gen_mxu_q16scop(ctx);
+ break;
default:
return false;
}
--
2.40.0
- [PATCH 16/33] target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions, (continued)
- [PATCH 16/33] target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions, Siarhei Volkau, 2023/06/08
- [PATCH 18/33] target/mips: Add emulation of MXU Q16ACC Q16ACCM D16ASUM instructions, Siarhei Volkau, 2023/06/08
- [PATCH 19/33] target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC instructions, Siarhei Volkau, 2023/06/08
- [PATCH 22/33] target/mips: Add emulation of MXU S32MUL S32MULU S32EXTR S32EXTRV insns, Siarhei Volkau, 2023/06/08
- [PATCH 08/33] target/mips: Add emulation of Q8ADD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 09/33] target/mips: Add emulation of MXU S32CPS D16CPS Q8ABD Q16SAT insns, Siarhei Volkau, 2023/06/08
- [PATCH 10/33] target/mips: Add emulation of MXU D16MULF D16MULE instructions, Siarhei Volkau, 2023/06/08
- [PATCH 23/33] target/mips: Add emulation of MXU S32ALN S32LUI insns, Siarhei Volkau, 2023/06/08
- [PATCH 27/33] target/mips: Add emulation of MXU D32/Q16- SLLV/SLRV/SARV instructions, Siarhei Volkau, 2023/06/08
- [PATCH 29/33] target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions, Siarhei Volkau, 2023/06/08
- [PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction,
Siarhei Volkau <=
- [PATCH 31/33] target/mips: Add emulation of MXU Q8MADL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 33/33] target/mips: Add emulation of MXU Q8SAD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 20/33] target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions, Siarhei Volkau, 2023/06/08
- [PATCH 21/33] target/mips: Add emulation of MXU S16LDD S16STD S16LDI S16SDI instructions, Siarhei Volkau, 2023/06/08
- [PATCH 24/33] target/mips: Add emulation of MXU D32SARL D32SARW instructions, Siarhei Volkau, 2023/06/08
- [PATCH 14/33] target/mips: Add emulation of MXU Q16ADD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 26/33] target/mips: Add emulation of MXU Q16SLL Q16SLR Q16SAR instructions, Siarhei Volkau, 2023/06/08
- [PATCH 17/33] target/mips: Add emulation of MXU D32ADDC instruction, Siarhei Volkau, 2023/06/08
- [PATCH 28/33] target/mips: Add emulation of MXU S32/D16/Q8- MOVZ/MOVN instructions, Siarhei Volkau, 2023/06/08