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[PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction
From: |
Siarhei Volkau |
Subject: |
[PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction |
Date: |
Thu, 8 Jun 2023 13:42:21 +0300 |
The instruction shuffles 8 bytes in two registers by
one of 4 predefined patterns.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
target/mips/tcg/mxu_translate.c | 81 +++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index ea2768cd57..1e043908db 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -409,6 +409,7 @@ enum {
OPC_MXU__POOL21 = 0x3A,
OPC_MXU_Q16SCOP = 0x3B,
OPC_MXU_Q8MADL = 0x3C,
+ OPC_MXU_S32SFL = 0x3D,
};
@@ -3963,6 +3964,83 @@ static void gen_mxu_q16scop(DisasContext *ctx)
gen_store_mxu_gpr(t4, XRd);
}
+/*
+ * S32SFL XRa, XRd, XRb, XRc
+ * Shuffle bytes according to one of four patterns.
+ */
+static void gen_mxu_s32sfl(DisasContext *ctx)
+{
+ uint32_t XRd, XRc, XRb, XRa, ptn2;
+
+ XRd = extract32(ctx->opcode, 18, 4);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+ ptn2 = extract32(ctx->opcode, 24, 2);
+
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t0, XRb);
+ gen_load_mxu_gpr(t1, XRc);
+
+ switch (ptn2) {
+ case 0:
+ tcg_gen_andi_tl(t2, t0, 0xff000000);
+ tcg_gen_andi_tl(t3, t1, 0x000000ff);
+ tcg_gen_deposit_tl(t3, t3, t0, 8, 8);
+ tcg_gen_shri_tl(t0, t0, 8);
+ tcg_gen_shri_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t3, t3, t0, 24, 8);
+ tcg_gen_deposit_tl(t3, t3, t1, 16, 8);
+ tcg_gen_shri_tl(t0, t0, 8);
+ tcg_gen_shri_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t2, t2, t0, 8, 8);
+ tcg_gen_deposit_tl(t2, t2, t1, 0, 8);
+ tcg_gen_shri_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t2, t2, t1, 16, 8);
+ break;
+ case 1:
+ tcg_gen_andi_tl(t2, t0, 0xff000000);
+ tcg_gen_andi_tl(t3, t1, 0x000000ff);
+ tcg_gen_deposit_tl(t3, t3, t0, 16, 8);
+ tcg_gen_shri_tl(t0, t0, 8);
+ tcg_gen_shri_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t2, t2, t0, 16, 8);
+ tcg_gen_deposit_tl(t2, t2, t1, 0, 8);
+ tcg_gen_shri_tl(t0, t0, 8);
+ tcg_gen_shri_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t3, t3, t0, 24, 8);
+ tcg_gen_deposit_tl(t3, t3, t1, 8, 8);
+ tcg_gen_shri_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t2, t2, t1, 8, 8);
+ break;
+ case 2:
+ tcg_gen_andi_tl(t2, t0, 0xff00ff00);
+ tcg_gen_andi_tl(t3, t1, 0x00ff00ff);
+ tcg_gen_deposit_tl(t3, t3, t0, 8, 8);
+ tcg_gen_shri_tl(t0, t0, 16);
+ tcg_gen_shri_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t2, t2, t1, 0, 8);
+ tcg_gen_deposit_tl(t3, t3, t0, 24, 8);
+ tcg_gen_shri_tl(t1, t1, 16);
+ tcg_gen_deposit_tl(t2, t2, t1, 16, 8);
+ break;
+ case 3:
+ tcg_gen_andi_tl(t2, t0, 0xffff0000);
+ tcg_gen_andi_tl(t3, t1, 0x0000ffff);
+ tcg_gen_shri_tl(t1, t1, 16);
+ tcg_gen_deposit_tl(t2, t2, t1, 0, 16);
+ tcg_gen_deposit_tl(t3, t3, t0, 16, 16);
+ break;
+ }
+
+ gen_store_mxu_gpr(t2, XRa);
+ gen_store_mxu_gpr(t3, XRd);
+}
+
/*
* MXU instruction category: align
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -4961,6 +5039,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
case OPC_MXU_Q8MADL:
gen_mxu_q8madl(ctx);
break;
+ case OPC_MXU_S32SFL:
+ gen_mxu_s32sfl(ctx);
+ break;
default:
return false;
}
--
2.40.0
- [PATCH 19/33] target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC instructions, (continued)
- [PATCH 19/33] target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC instructions, Siarhei Volkau, 2023/06/08
- [PATCH 22/33] target/mips: Add emulation of MXU S32MUL S32MULU S32EXTR S32EXTRV insns, Siarhei Volkau, 2023/06/08
- [PATCH 08/33] target/mips: Add emulation of Q8ADD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 09/33] target/mips: Add emulation of MXU S32CPS D16CPS Q8ABD Q16SAT insns, Siarhei Volkau, 2023/06/08
- [PATCH 10/33] target/mips: Add emulation of MXU D16MULF D16MULE instructions, Siarhei Volkau, 2023/06/08
- [PATCH 23/33] target/mips: Add emulation of MXU S32ALN S32LUI insns, Siarhei Volkau, 2023/06/08
- [PATCH 27/33] target/mips: Add emulation of MXU D32/Q16- SLLV/SLRV/SARV instructions, Siarhei Volkau, 2023/06/08
- [PATCH 29/33] target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions, Siarhei Volkau, 2023/06/08
- [PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction, Siarhei Volkau, 2023/06/08
- [PATCH 31/33] target/mips: Add emulation of MXU Q8MADL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction,
Siarhei Volkau <=
- [PATCH 33/33] target/mips: Add emulation of MXU Q8SAD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 20/33] target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions, Siarhei Volkau, 2023/06/08
- [PATCH 21/33] target/mips: Add emulation of MXU S16LDD S16STD S16LDI S16SDI instructions, Siarhei Volkau, 2023/06/08
- [PATCH 24/33] target/mips: Add emulation of MXU D32SARL D32SARW instructions, Siarhei Volkau, 2023/06/08
- [PATCH 14/33] target/mips: Add emulation of MXU Q16ADD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 26/33] target/mips: Add emulation of MXU Q16SLL Q16SLR Q16SAR instructions, Siarhei Volkau, 2023/06/08
- [PATCH 17/33] target/mips: Add emulation of MXU D32ADDC instruction, Siarhei Volkau, 2023/06/08
- [PATCH 28/33] target/mips: Add emulation of MXU S32/D16/Q8- MOVZ/MOVN instructions, Siarhei Volkau, 2023/06/08
- [PATCH 25/33] target/mips: Add emulation of MXU D32SLL D32SLR D32SAR instructions, Siarhei Volkau, 2023/06/08