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[PATCH 17/33] target/mips: Add emulation of MXU D32ADDC instruction
From: |
Siarhei Volkau |
Subject: |
[PATCH 17/33] target/mips: Add emulation of MXU D32ADDC instruction |
Date: |
Thu, 8 Jun 2023 13:42:06 +0300 |
The instruction adds two 32-bit values with respect
to corresponding carry flags in MXU_CR.
XRa += XRb + LeftCarry flag;
XRd += XRc + RightCarry flag;
Suddenly, it doesn't modify carry flags as a result of addition.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
target/mips/tcg/mxu_translate.c | 39 +++++++++++++++++++++++++++------
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 56c894f4c7..2b677407d5 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -270,7 +270,7 @@
* │ 13..10
* ├─ 010111 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32SDIV
* │ └─ 0001 ─ OPC_MXU_S32SDIVR
- * ├─ 011000 ─ OPC_MXU_D32ADD
+ * ├─ 011000 ─ OPC_MXU_D32ADD (catches D32ADDC too)
* │ 23..22
* MXU ├─ 011001 ─ OPC_MXU__POOL12 ─┬─ 00 ─ OPC_MXU_D32ACC
* opcodes ─┤ ├─ 01 ─ OPC_MXU_D32ACCM
@@ -2262,14 +2262,17 @@ static void gen_mxu_q16add(DisasContext *ctx)
/*
* D32ADD XRa, XRb, XRc, XRd, aptn2 - Double
- * 32 bit pattern addition/subtraction.
+ * 32 bit pattern addition/subtraction, set carry.
+ *
+ * D32ADDC XRa, XRb, XRc, XRd, aptn2 - Double
+ * 32 bit pattern addition/subtraction with carry.
*/
static void gen_mxu_d32add(DisasContext *ctx)
{
- uint32_t aptn2, pad, XRc, XRb, XRa, XRd;
+ uint32_t aptn2, addc, XRc, XRb, XRa, XRd;
aptn2 = extract32(ctx->opcode, 24, 2);
- pad = extract32(ctx->opcode, 22, 2);
+ addc = extract32(ctx->opcode, 22, 2);
XRd = extract32(ctx->opcode, 18, 4);
XRc = extract32(ctx->opcode, 14, 4);
XRb = extract32(ctx->opcode, 10, 4);
@@ -2278,15 +2281,37 @@ static void gen_mxu_d32add(DisasContext *ctx)
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- TCGv carry = tcg_temp_new();
TCGv cr = tcg_temp_new();
- if (unlikely(pad != 0)) {
- /* opcode padding incorrect -> do nothing */
+ if (unlikely(addc > 1)) {
+ /* opcode incorrect -> do nothing */
+ } else if (addc == 1) {
+ if (unlikely(XRa == 0 && XRd == 0)) {
+ /* destinations are zero register -> do nothing */
+ } else {
+ /* FIXME ??? What if XRa == XRd ??? */
+ /* aptn2 is unused here */
+ gen_load_mxu_gpr(t0, XRb);
+ gen_load_mxu_gpr(t1, XRc);
+ gen_load_mxu_cr(cr);
+ if (XRa != 0) {
+ tcg_gen_extract_tl(t2, cr, 31, 1);
+ tcg_gen_add_tl(t0, t0, t2);
+ tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
+ }
+ if (XRd != 0) {
+ tcg_gen_extract_tl(t2, cr, 30, 1);
+ tcg_gen_add_tl(t1, t1, t2);
+ tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);
+ }
+ }
} else if (unlikely(XRa == 0 && XRd == 0)) {
/* destinations are zero register -> do nothing */
} else {
/* common case */
+ /* FIXME ??? What if XRa == XRd ??? */
+ TCGv carry = tcg_temp_new();
+
gen_load_mxu_gpr(t0, XRb);
gen_load_mxu_gpr(t1, XRc);
gen_load_mxu_cr(cr);
--
2.40.0
- [PATCH 29/33] target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions, (continued)
- [PATCH 29/33] target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions, Siarhei Volkau, 2023/06/08
- [PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction, Siarhei Volkau, 2023/06/08
- [PATCH 31/33] target/mips: Add emulation of MXU Q8MADL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 33/33] target/mips: Add emulation of MXU Q8SAD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 20/33] target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions, Siarhei Volkau, 2023/06/08
- [PATCH 21/33] target/mips: Add emulation of MXU S16LDD S16STD S16LDI S16SDI instructions, Siarhei Volkau, 2023/06/08
- [PATCH 24/33] target/mips: Add emulation of MXU D32SARL D32SARW instructions, Siarhei Volkau, 2023/06/08
- [PATCH 14/33] target/mips: Add emulation of MXU Q16ADD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 26/33] target/mips: Add emulation of MXU Q16SLL Q16SLR Q16SAR instructions, Siarhei Volkau, 2023/06/08
- [PATCH 17/33] target/mips: Add emulation of MXU D32ADDC instruction,
Siarhei Volkau <=
- [PATCH 28/33] target/mips: Add emulation of MXU S32/D16/Q8- MOVZ/MOVN instructions, Siarhei Volkau, 2023/06/08
- [PATCH 25/33] target/mips: Add emulation of MXU D32SLL D32SLR D32SAR instructions, Siarhei Volkau, 2023/06/08