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[PULL 01/29] pnv/xive2: Add definition for TCTXT Config register
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 01/29] pnv/xive2: Add definition for TCTXT Config register |
Date: |
Sat, 10 Jun 2023 10:31:04 -0300 |
From: Frederic Barrat <fbarrat@linux.ibm.com>
Add basic read/write support for the TCTXT Config register on P10. qemu
doesn't do anything with it yet, but it avoids logging a guest error
when skiboot configures the fused-core state:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
[ 0.131670000,5] XIVE: [ IC 00 ] Initializing XIVE block ID 0...
XIVE[0] - TCTXT: invalid read @140
XIVE[0] - TCTXT: invalid write @140
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-2-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/intc/pnv_xive2.c | 8 +++++++-
hw/intc/pnv_xive2_regs.h | 4 ++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 7176d70234..889e409929 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1265,6 +1265,9 @@ static uint64_t pnv_xive2_ic_tctxt_read(void *opaque,
hwaddr offset,
case TCTXT_EN1_RESET:
val = xive->tctxt_regs[TCTXT_EN1 >> 3];
break;
+ case TCTXT_CFG:
+ val = xive->tctxt_regs[reg];
+ break;
default:
xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset);
}
@@ -1276,6 +1279,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr
offset,
uint64_t val, unsigned size)
{
PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t reg = offset >> 3;
switch (offset) {
/*
@@ -1297,7 +1301,9 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr
offset,
case TCTXT_EN1_RESET:
xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val;
break;
-
+ case TCTXT_CFG:
+ xive->tctxt_regs[reg] = val;
+ break;
default:
xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset);
return;
diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
index 0c096e4adb..8f1e0a1fde 100644
--- a/hw/intc/pnv_xive2_regs.h
+++ b/hw/intc/pnv_xive2_regs.h
@@ -405,6 +405,10 @@
#define X_TCTXT_EN1_RESET 0x307
#define TCTXT_EN1_RESET 0x038
+/* TCTXT Config register */
+#define X_TCTXT_CFG 0x328
+#define TCTXT_CFG 0x140
+
/*
* VSD Tables
*/
--
2.40.1
- [PULL 00/29] ppc queue, Daniel Henrique Barboza, 2023/06/10
- [PULL 01/29] pnv/xive2: Add definition for TCTXT Config register,
Daniel Henrique Barboza <=
- [PULL 04/29] pnv/xive2: Introduce macros to manipulate TIMA addresses, Daniel Henrique Barboza, 2023/06/10
- [PULL 03/29] pnv/xive2: Allow writes to the Physical Thread Enable registers, Daniel Henrique Barboza, 2023/06/10
- [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Daniel Henrique Barboza, 2023/06/10
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Peter Maydell, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Frederic Barrat, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/21
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Frederic Barrat, 2023/06/21
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/21