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Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports
From: |
Frederic Barrat |
Subject: |
Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports |
Date: |
Wed, 21 Jun 2023 17:18:51 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.1 |
On 21/06/2023 09:18, Cédric Le Goater wrote:
The XIVE2 TM ops are implemented with a shortcut (See the TODO in
pnv_xive2_tm_*()). We could
1. extend xive_tctx_tm_write/read with a 'bool gen1_tima_os' parameter:
xive_tctx_tm_write(xptr, tctx, offset, value, size, gen1_tima_os);
and use the bool in xive_tm_find_op() to select a XiveTmOp array.
The new xive2_tm_operations[] would be defined as xive_tm_operations[]
but with an override of HV_PUSH_OS_CTX_OFFSET and
HV_PULL_OS_CTX_OFFSET.
2. or extend the XivePresenterClass with a get_config() handler like it
was done for Xive2RouterClass().
3. or introduce an array of XiveTmOp under XivePresenterClass defined by
the controller variant.
In any case, we need a new xive2_tm_operations[] for the XIVE2 TM register
layout. Option 1 is simpler I think.
I was also leaning on introducing a xive2_tm_operations[] array of
operations to fix it correctly.
While I agree it's the simplest, I'm not fond of (1), since we'd need to
carry that extra parameter to xive_tm_find_op(). Admittedly it's just
one extra level, but I went with something which is hopefully what you
had in mind for (2). I like that we can easily extend it in the future.
This would also "fix" the indirect ops in XIVE2, not that we care much
but it will be cleaner.
I'm not sure I see what you mean here. It cleans up nicely
pnv_xive2_tm_read/write(), but is that really what you had in mind?
Something related I notice is that when doing an indirect access to the
TIMA through the IC BAR, we call the TIMA access functions with a NULL
reference to the presenter:
static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset,
unsigned size)
{
PnvXive2 *xive = PNV_XIVE2(opaque);
...
tctx = pnv_xive2_get_indirect_tctx(xive, pir);
if (tctx) {
val = xive_tctx_tm_read(NULL, tctx, offset, size);
}
We seem to mostly ignore that first parameter in
xive_tctx_tm_read/write(). IIUC, the special ops will be checked with a
page offset matching ring 0 and won't match anything. Still, it seems a
bit dangerous and I was wondering:
1. can't we just create it from the PnvXive2 we have at hand?
2. in any case, isn't it always redundant with tctxt->presenter?
Fred
- [PULL 00/29] ppc queue, Daniel Henrique Barboza, 2023/06/10
- [PULL 01/29] pnv/xive2: Add definition for TCTXT Config register, Daniel Henrique Barboza, 2023/06/10
- [PULL 04/29] pnv/xive2: Introduce macros to manipulate TIMA addresses, Daniel Henrique Barboza, 2023/06/10
- [PULL 03/29] pnv/xive2: Allow writes to the Physical Thread Enable registers, Daniel Henrique Barboza, 2023/06/10
- [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Daniel Henrique Barboza, 2023/06/10
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Peter Maydell, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Frederic Barrat, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/20
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/21
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports,
Frederic Barrat <=
- Re: [PULL 05/29] pnv/xive2: Handle TIMA access through all ports, Cédric Le Goater, 2023/06/21
[PULL 02/29] pnv/xive2: Add definition for the ESB cache configuration register, Daniel Henrique Barboza, 2023/06/10
[PULL 06/29] target/ppc: Fix nested-hv HEAI delivery, Daniel Henrique Barboza, 2023/06/10
[PULL 07/29] pnv/xive2: Quiet down some error messages, Daniel Henrique Barboza, 2023/06/10
[PULL 08/29] target/ppc: Fix PMU hflags calculation, Daniel Henrique Barboza, 2023/06/10
[PULL 09/29] target/ppc: PMU do not clear MMCR0[FCECE] on performance monitor alert, Daniel Henrique Barboza, 2023/06/10
[PULL 10/29] target/ppc: Fix msgclrp interrupt type, Daniel Henrique Barboza, 2023/06/10
[PULL 11/29] target/ppc: Support directed privileged doorbell interrupt (SDOOR), Daniel Henrique Barboza, 2023/06/10
[PULL 12/29] target/ppc: PMU implement PERFM interrupts, Daniel Henrique Barboza, 2023/06/10
[PULL 13/29] target/ppc: Remove single use function, Daniel Henrique Barboza, 2023/06/10