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[PATCH v2 6/8] disas/riscv: Provide infrastructure for vendor extensions
From: |
Christoph Muellner |
Subject: |
[PATCH v2 6/8] disas/riscv: Provide infrastructure for vendor extensions |
Date: |
Mon, 12 Jun 2023 13:10:32 +0200 |
From: Christoph Müllner <christoph.muellner@vrull.eu>
A previous patch provides a pointer to the RISCVCPUConfig data.
Let's use this to add the necessary code for vendor extensions.
This patch does not change the current behaviour, but clearly
defines how vendor extension support can be added to the disassembler.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
disas/riscv.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index b6789ab92a..dc3bfb0123 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4700,9 +4700,33 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa,
uint64_t pc, rv_inst inst,
rv_decode dec = { 0 };
dec.pc = pc;
dec.inst = inst;
- dec.opcode_data = rvi_opcode_data;
dec.cfg = cfg;
- decode_inst_opcode(&dec, isa);
+
+ static const struct {
+ bool (*guard_func)(const RISCVCPUConfig *);
+ const rv_opcode_data *opcode_data;
+ void (*decode_func)(rv_decode *, rv_isa);
+ } decoders[] = {
+ { always_true_p, rvi_opcode_data, decode_inst_opcode },
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
+ bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func;
+ const rv_opcode_data *opcode_data = decoders[i].opcode_data;
+ void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func;
+
+ if (guard_func(cfg)) {
+ dec.opcode_data = opcode_data;
+ decode_func(&dec, isa);
+ if (dec.op != rv_op_illegal)
+ break;
+ }
+ }
+
+ if (dec.op == rv_op_illegal) {
+ dec.opcode_data = rvi_opcode_data;
+ }
+
decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa);
decode_inst_lift_pseudo(&dec);
--
2.40.1
- [PATCH v2 0/8] disas/riscv: Add vendor extension support, Christoph Muellner, 2023/06/12
- [PATCH v2 1/8] target/riscv: Use xl instead of mxl for disassemble, Christoph Muellner, 2023/06/12
- [PATCH v2 5/8] disas/riscv: Encapsulate opcode_data into decode, Christoph Muellner, 2023/06/12
- [PATCH v2 6/8] disas/riscv: Provide infrastructure for vendor extensions,
Christoph Muellner <=
- [PATCH v2 2/8] target/riscv: Factor out extension tests to cpu_cfg.h, Christoph Muellner, 2023/06/12
- [PATCH v2 4/8] disas/riscv: Make rv_op_illegal a shared enum value, Christoph Muellner, 2023/06/12
- [PATCH v2 7/8] disas/riscv: Add support for XVentanaCondOps, Christoph Muellner, 2023/06/12
- [PATCH v2 3/8] disas/riscv: Move types/constants to new header file, Christoph Muellner, 2023/06/12
- [PATCH v2 8/8] disas/riscv: Add support for XThead* instructions, Christoph Muellner, 2023/06/12