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[PATCH v3 1/5] target/microblaze: Define TCG_GUEST_DEFAULT_MO
From: |
Richard Henderson |
Subject: |
[PATCH v3 1/5] target/microblaze: Define TCG_GUEST_DEFAULT_MO |
Date: |
Mon, 19 Jun 2023 16:23:29 +0200 |
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling MTTCG.
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Fixes: d449561b130 ("configure: microblaze: Enable mttcg")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 88324d0bc1..b474abcc2a 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
+/* MicroBlaze is always in-order. */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
typedef struct CPUArchState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
--
2.34.1
- [PATCH v3 0/5] tcg: Issue memory barriers for guest memory model, Richard Henderson, 2023/06/19
- [PATCH v3 1/5] target/microblaze: Define TCG_GUEST_DEFAULT_MO,
Richard Henderson <=
- [PATCH v3 2/5] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode, Richard Henderson, 2023/06/19
- [PATCH v3 4/5] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2023/06/19
- [PATCH v3 5/5] accel/tcg: Remove check_tcg_memory_orders_compatible, Richard Henderson, 2023/06/19
- [PATCH v3 3/5] tcg: Elide memory barriers implied by the host memory model, Richard Henderson, 2023/06/19
- Re: [PATCH v3 0/5] tcg: Issue memory barriers for guest memory model, Richard Henderson, 2023/06/19