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[PATCH v3 2/5] tcg: Do not elide memory barriers for !CF_PARALLEL in sys
From: |
Richard Henderson |
Subject: |
[PATCH v3 2/5] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode |
Date: |
Mon, 19 Jun 2023 16:23:30 +0200 |
The virtio devices require proper memory ordering between
the vcpus and the iothreads.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c07de5d9f8..7aadb37756 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -102,7 +102,19 @@ void tcg_gen_br(TCGLabel *l)
void tcg_gen_mb(TCGBar mb_type)
{
- if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) {
+#ifdef CONFIG_USER_ONLY
+ bool parallel = tcg_ctx->gen_tb->cflags & CF_PARALLEL;
+#else
+ /*
+ * It is tempting to elide the barrier in a uniprocessor context.
+ * However, even with a single cpu we have i/o threads running in
+ * parallel, and lack of memory order can result in e.g. virtio
+ * queue entries being read incorrectly.
+ */
+ bool parallel = true;
+#endif
+
+ if (parallel) {
tcg_gen_op1(INDEX_op_mb, mb_type);
}
}
--
2.34.1
- [PATCH v3 0/5] tcg: Issue memory barriers for guest memory model, Richard Henderson, 2023/06/19
- [PATCH v3 1/5] target/microblaze: Define TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/06/19
- [PATCH v3 2/5] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode,
Richard Henderson <=
- [PATCH v3 4/5] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2023/06/19
- [PATCH v3 5/5] accel/tcg: Remove check_tcg_memory_orders_compatible, Richard Henderson, 2023/06/19
- [PATCH v3 3/5] tcg: Elide memory barriers implied by the host memory model, Richard Henderson, 2023/06/19
- Re: [PATCH v3 0/5] tcg: Issue memory barriers for guest memory model, Richard Henderson, 2023/06/19
- Re: [PATCH v3 0/5] tcg: Issue memory barriers for guest memory model, Richard Henderson, 2023/06/26