Re: [PATCH v3 1/5] target/microblaze: Define TCG_GUEST_DEFAULT_MO

[Philippe Mathieu-Daudé]

On 19/6/23 16:23, Richard Henderson wrote:
> The microblaze architecture does not reorder instructions.
> While there is an MBAR wait-for-data-access instruction,
> this concerns synchronizing with DMA.
>
> This should have been defined when enabling MTTCG.
>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> Fixes: d449561b130 ("configure: microblaze: Enable mttcg")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/microblaze/cpu.h | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 88324d0bc1..b474abcc2a 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -24,6 +24,9 @@
>   #include "exec/cpu-defs.h"
>   #include "qemu/cpu-float.h"
>   
> +/* MicroBlaze is always in-order. */
> +#define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL

Targets missing such definition:

- cris
- m68k
- nios2
- rx
- sh4
- sparc/64 (!)
- tricore

I expect targets designed for embedded systems
to be in-order for power efficiency.

What about having each target being explicit about that,
having a build failure if TCG_GUEST_DEFAULT_MO is not defined,
instead of the '#ifdef TCG_GUEST_DEFAULT_MO' in accel/tcg/?