[PATCH v2 08/10] target/i386: implement 32-bit SYSCALL for linux-user

[Paolo Bonzini]

TCG supports both 32-bit and 64-bit SYSCALL, but the linux-user
code only exposes it for 64-bit.  The ABI is the same as "int $80",
so expose it even for 32-bit emulators, where it can be used if the
vendor is specified as AMD.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 linux-user/i386/cpu_loop.c        | 3 +++
 target/i386/cpu.c                 | 8 +++++++-
 target/i386/helper.h              | 2 +-
 target/i386/tcg/translate.c       | 2 +-
 target/i386/tcg/user/seg_helper.c | 2 --
 5 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
index 2d0918a93ff..6908bad14aa 100644
--- a/linux-user/i386/cpu_loop.c
+++ b/linux-user/i386/cpu_loop.c
@@ -211,6 +211,9 @@ void cpu_loop(CPUX86State *env)
 
         switch(trapnr) {
         case 0x80:
+#ifdef TARGET_ABI32
+        case EXCP_SYSCALL:
+#endif
             /* linux syscall from int $0x80 */
             ret = do_syscall(env,
                              env->regs[R_EAX],
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 978d24b5ec7..934360e4091 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -642,10 +642,16 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 #define TCG_EXT2_X86_64_FEATURES 0
 #endif
 
+#if defined CONFIG_SOFTMMU || defined CONFIG_LINUX_USER
+#define TCG_EXT2_NOBSD_FEATURES CPUID_EXT2_SYSCALL
+#else
+#define TCG_EXT2_NOBSD_FEATURES 0
+#endif
+
 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
-          TCG_EXT2_X86_64_FEATURES)
+          TCG_EXT2_NOBSD_FEATURES | TCG_EXT2_X86_64_FEATURES)
 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
           CPUID_EXT3_3DNOWPREFETCH)
diff --git a/target/i386/helper.h b/target/i386/helper.h
index e627a931073..c2e86c6119c 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -51,8 +51,8 @@ DEF_HELPER_FLAGS_2(get_dr, TCG_CALL_NO_WG, tl, env, int)
 
 DEF_HELPER_1(sysenter, void, env)
 DEF_HELPER_2(sysexit, void, env, int)
-#ifdef TARGET_X86_64
 DEF_HELPER_2(syscall, void, env, int)
+#ifdef TARGET_X86_64
 DEF_HELPER_2(sysret, void, env, int)
 #endif
 DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index c58f5f24ab3..0ddb689444e 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -5682,7 +5682,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
             s->base.is_jmp = DISAS_EOB_ONLY;
         }
         break;
-#ifdef TARGET_X86_64
     case 0x105: /* syscall */
         /* For Intel SYSCALL is only valid in 64-bit */
         if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) {
@@ -5696,6 +5695,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
            generated after one has entered CPL0 if TF is set in FMASK.  */
         gen_eob_worker(s, false, true);
         break;
+#ifdef TARGET_X86_64
     case 0x107: /* sysret */
         if (!PE(s) || CPL(s) != 0) {
             gen_exception_gpf(s);
diff --git a/target/i386/tcg/user/seg_helper.c 
b/target/i386/tcg/user/seg_helper.c
index 67481b0aa8e..c45f2ac2ba6 100644
--- a/target/i386/tcg/user/seg_helper.c
+++ b/target/i386/tcg/user/seg_helper.c
@@ -26,7 +26,6 @@
 #include "tcg/helper-tcg.h"
 #include "tcg/seg_helper.h"
 
-#ifdef TARGET_X86_64
 void helper_syscall(CPUX86State *env, int next_eip_addend)
 {
     CPUState *cs = env_cpu(env);
@@ -36,7 +35,6 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
     env->exception_next_eip = env->eip + next_eip_addend;
     cpu_loop_exit(cs);
 }
-#endif /* TARGET_X86_64 */
 
 /*
  * fake user mode interrupt. is_int is TRUE if coming from the int
-- 
2.40.1