[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 14/20] target/tricore: Introduce DISAS_TARGET_EXIT
From: |
Bastian Koppelmann |
Subject: |
[PULL 14/20] target/tricore: Introduce DISAS_TARGET_EXIT |
Date: |
Wed, 21 Jun 2023 18:14:16 +0200 |
this replaces all calls to tcg_gen_exit_tb() and moves them to
tricore_tb_stop().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-3-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index cca52c75b2..ef74e9f234 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -37,6 +37,7 @@
#include "exec/helper-info.c.inc"
#undef HELPER_H
+#define DISAS_EXIT DISAS_TARGET_0
/*
* TCG registers
@@ -2836,6 +2837,7 @@ static void gen_goto_tb(DisasContext *ctx, int n,
target_ulong dest)
gen_save_pc(dest);
tcg_gen_lookup_and_goto_ptr();
}
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static void generate_trap(DisasContext *ctx, int class, int tin)
@@ -2896,8 +2898,7 @@ static void gen_fret(DisasContext *ctx)
tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
tcg_gen_mov_tl(cpu_PC, temp);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ ctx->base.is_jmp = DISAS_EXIT;
}
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
@@ -2996,12 +2997,12 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc, int r1,
/* SR-format jumps */
case OPC1_16_SR_JI:
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
- tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_32_SYS_RET:
case OPC2_16_SR_RET:
gen_helper_ret(cpu_env);
- tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_EXIT;
break;
/* B-format */
case OPC1_32_B_CALLA:
@@ -3153,7 +3154,6 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc, int r1,
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
- ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -3495,8 +3495,7 @@ static void decode_sr_system(DisasContext *ctx)
break;
case OPC2_16_SR_RFE:
gen_helper_rfe(cpu_env);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_16_SR_DEBUG:
/* raise EXCP_DEBUG */
@@ -6078,8 +6077,7 @@ static void decode_rr_idirect(DisasContext *ctx)
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ ctx->base.is_jmp = DISAS_EXIT;
}
static void decode_rr_divide(DisasContext *ctx)
@@ -7915,8 +7913,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_RFE:
gen_helper_rfe(cpu_env);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_32_SYS_RFM:
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
@@ -7928,8 +7925,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
gen_helper_rfm(cpu_env);
gen_set_label(l1);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ ctx->base.is_jmp = DISAS_EXIT;
} else {
/* generate privilege trap */
}
@@ -8391,6 +8387,9 @@ static void tricore_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
case DISAS_TOO_MANY:
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
+ case DISAS_EXIT:
+ tcg_gen_exit_tb(NULL, 0);
+ break;
case DISAS_NORETURN:
break;
default:
--
2.40.1
- [PULL 04/20] target/tricore: Add crc32l.w insn, (continued)
- [PULL 04/20] target/tricore: Add crc32l.w insn, Bastian Koppelmann, 2023/06/21
- [PULL 05/20] target/tricore: Add crc32.b insn, Bastian Koppelmann, 2023/06/21
- [PULL 06/20] target/tricore: Add shuffle insn, Bastian Koppelmann, 2023/06/21
- [PULL 07/20] target/tricore: Implement SYCSCALL insn, Bastian Koppelmann, 2023/06/21
- [PULL 08/20] target/tricore: Add DISABLE insn variant, Bastian Koppelmann, 2023/06/21
- [PULL 09/20] target/tricore: Fix out-of-bounds index in imask instruction, Bastian Koppelmann, 2023/06/21
- [PULL 10/20] target/tricore: Correctly fix saving PSW.CDE to CSA on call, Bastian Koppelmann, 2023/06/21
- [PULL 11/20] target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs, Bastian Koppelmann, 2023/06/21
- [PULL 12/20] target/tricore: Fix helper_ret() not correctly restoring PSW, Bastian Koppelmann, 2023/06/21
- [PULL 13/20] target/tricore: Fix RR_JLI clobbering reg A[11], Bastian Koppelmann, 2023/06/21
- [PULL 14/20] target/tricore: Introduce DISAS_TARGET_EXIT,
Bastian Koppelmann <=
- [PULL 15/20] target/tricore: ENABLE exit to main-loop, Bastian Koppelmann, 2023/06/21
- [PULL 16/20] target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr(), Bastian Koppelmann, 2023/06/21
- [PULL 17/20] target/tricore: Introduce priv tb flag, Bastian Koppelmann, 2023/06/21
- [PULL 18/20] target/tricore: Implement privilege level for all insns, Bastian Koppelmann, 2023/06/21
- [PULL 19/20] target/tricore: Honour privilege changes on PSW write, Bastian Koppelmann, 2023/06/21
- [PULL 20/20] target/tricore: Fix ICR.IE offset in RESTORE insn, Bastian Koppelmann, 2023/06/21
- Re: [PULL 00/20] tricore queue, Richard Henderson, 2023/06/21