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[PULL 19/20] target/tricore: Honour privilege changes on PSW write
From: |
Bastian Koppelmann |
Subject: |
[PULL 19/20] target/tricore: Honour privilege changes on PSW write |
Date: |
Wed, 21 Jun 2023 18:14:21 +0200 |
the CPU can change the privilege level by writing the corresponding bits
in PSW. If this happens all instructions after this 'mtcr' in the TB are
translated with the wrong privilege level. So we have to exit to the
cpu_loop() and start translating again with the new privilege level.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-8-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 82b61e912e..9e408f44ec 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -334,7 +334,6 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
}
-
/* We generate loads and store to core special function register (csfr) through
the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
makros R, A and E, which allow read-only, all and endinit protected access.
@@ -382,6 +381,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
gen_helper_psw_write(cpu_env, r1);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
switch (offset) {
#include "csfr.h.inc"
--
2.40.1
- Re: [PULL 09/20] target/tricore: Fix out-of-bounds index in imask instruction, (continued)
- [PULL 10/20] target/tricore: Correctly fix saving PSW.CDE to CSA on call, Bastian Koppelmann, 2023/06/21
- [PULL 11/20] target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs, Bastian Koppelmann, 2023/06/21
- [PULL 12/20] target/tricore: Fix helper_ret() not correctly restoring PSW, Bastian Koppelmann, 2023/06/21
- [PULL 13/20] target/tricore: Fix RR_JLI clobbering reg A[11], Bastian Koppelmann, 2023/06/21
- [PULL 14/20] target/tricore: Introduce DISAS_TARGET_EXIT, Bastian Koppelmann, 2023/06/21
- [PULL 15/20] target/tricore: ENABLE exit to main-loop, Bastian Koppelmann, 2023/06/21
- [PULL 16/20] target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr(), Bastian Koppelmann, 2023/06/21
- [PULL 17/20] target/tricore: Introduce priv tb flag, Bastian Koppelmann, 2023/06/21
- [PULL 18/20] target/tricore: Implement privilege level for all insns, Bastian Koppelmann, 2023/06/21
- [PULL 19/20] target/tricore: Honour privilege changes on PSW write,
Bastian Koppelmann <=
- [PULL 20/20] target/tricore: Fix ICR.IE offset in RESTORE insn, Bastian Koppelmann, 2023/06/21
- Re: [PULL 00/20] tricore queue, Richard Henderson, 2023/06/21