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[PATCH v3 08/16] tcg/loongarch64: Lower mul_vec to vmul
From: |
Jiajie Chen |
Subject: |
[PATCH v3 08/16] tcg/loongarch64: Lower mul_vec to vmul |
Date: |
Sat, 2 Sep 2023 13:02:08 +0800 |
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 8 ++++++++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 1e196bb68f..6905775698 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1665,6 +1665,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const LoongArchInsn neg_vec_insn[4] = {
OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D
};
+ static const LoongArchInsn mul_vec_insn[4] = {
+ OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D
+ };
a0 = args[0];
a1 = args[1];
@@ -1798,6 +1801,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_neg_vec:
tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1));
break;
+ case INDEX_op_mul_vec:
+ tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2));
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1824,6 +1830,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_nor_vec:
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
+ case INDEX_op_mul_vec:
return 1;
default:
return 0;
@@ -1998,6 +2005,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
case INDEX_op_nor_vec:
+ case INDEX_op_mul_vec:
return C_O1_I2(w, w, w);
case INDEX_op_not_vec:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 64c72d0857..2c2266ed31 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -185,7 +185,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_nand_vec 0
#define TCG_TARGET_HAS_nor_vec 1
#define TCG_TARGET_HAS_eqv_vec 0
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
--
2.42.0
- [PATCH v3 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX, (continued)
- [PATCH v3 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX, Jiajie Chen, 2023/09/02
- [PATCH v3 03/16] tcg: pass vece to tcg_target_const_match(), Jiajie Chen, 2023/09/02
- [PATCH v3 01/16] tcg/loongarch64: Import LSX instructions, Jiajie Chen, 2023/09/02
- [PATCH v3 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt, Jiajie Chen, 2023/09/02
- [PATCH v3 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub, Jiajie Chen, 2023/09/02
- [PATCH v3 07/16] tcg/loongarch64: Lower neg_vec to vneg, Jiajie Chen, 2023/09/02
- [PATCH v3 06/16] tcg/loongarch64: Lower vector bitwise operations, Jiajie Chen, 2023/09/02
- [PATCH v3 08/16] tcg/loongarch64: Lower mul_vec to vmul,
Jiajie Chen <=
- [PATCH v3 10/16] tcg/loongarch64: Lower vector saturated ops, Jiajie Chen, 2023/09/02
- [PATCH v3 09/16] tcg/loongarch64: Lower vector min max ops, Jiajie Chen, 2023/09/02
- [PATCH v3 11/16] tcg/loongarch64: Lower vector shift vector ops, Jiajie Chen, 2023/09/02
- [PATCH v3 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel, Jiajie Chen, 2023/09/02
- [PATCH v3 13/16] tcg/loongarch64: Lower vector shift integer ops, Jiajie Chen, 2023/09/02
- [PATCH v3 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX, Jiajie Chen, 2023/09/02
- [PATCH v3 15/16] tcg/loongarch64: Lower rotli_vec to vrotri, Jiajie Chen, 2023/09/02
- [PATCH v3 16/16] tcg/loongarch64: Implement 128-bit load & store, Jiajie Chen, 2023/09/02