[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 15/16] tcg/loongarch64: Lower rotli_vec to vrotri
From: |
Jiajie Chen |
Subject: |
[PATCH v3 15/16] tcg/loongarch64: Lower rotli_vec to vrotri |
Date: |
Sat, 2 Sep 2023 13:02:15 +0800 |
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 21 +++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 95359b1757..2b001598e2 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1901,6 +1901,26 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1,
temp_vec));
break;
+ case INDEX_op_rotli_vec:
+ /* rotli_vec a1, a2 = rotri_vec a1, -a2 */
+ a2 = extract32(-a2, 0, 3 + vece);
+ switch (vece) {
+ case MO_8:
+ tcg_out_opc_vrotri_b(s, a0, a1, a2);
+ break;
+ case MO_16:
+ tcg_out_opc_vrotri_h(s, a0, a1, a2);
+ break;
+ case MO_32:
+ tcg_out_opc_vrotri_w(s, a0, a1, a2);
+ break;
+ case MO_64:
+ tcg_out_opc_vrotri_d(s, a0, a1, a2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
case INDEX_op_bitsel_vec:
/* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
@@ -2139,6 +2159,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
+ case INDEX_op_rotli_vec:
return C_O1_I1(w, w);
case INDEX_op_bitsel_vec:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index d5c69bc192..67b0a95532 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -189,7 +189,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
-#define TCG_TARGET_HAS_roti_vec 0
+#define TCG_TARGET_HAS_roti_vec 1
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 1
#define TCG_TARGET_HAS_sat_vec 1
--
2.42.0
- Re: [PATCH v3 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub, (continued)
- [PATCH v3 07/16] tcg/loongarch64: Lower neg_vec to vneg, Jiajie Chen, 2023/09/02
- [PATCH v3 06/16] tcg/loongarch64: Lower vector bitwise operations, Jiajie Chen, 2023/09/02
- [PATCH v3 08/16] tcg/loongarch64: Lower mul_vec to vmul, Jiajie Chen, 2023/09/02
- [PATCH v3 10/16] tcg/loongarch64: Lower vector saturated ops, Jiajie Chen, 2023/09/02
- [PATCH v3 09/16] tcg/loongarch64: Lower vector min max ops, Jiajie Chen, 2023/09/02
- [PATCH v3 11/16] tcg/loongarch64: Lower vector shift vector ops, Jiajie Chen, 2023/09/02
- [PATCH v3 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel, Jiajie Chen, 2023/09/02
- [PATCH v3 13/16] tcg/loongarch64: Lower vector shift integer ops, Jiajie Chen, 2023/09/02
- [PATCH v3 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX, Jiajie Chen, 2023/09/02
- [PATCH v3 15/16] tcg/loongarch64: Lower rotli_vec to vrotri,
Jiajie Chen <=
- [PATCH v3 16/16] tcg/loongarch64: Implement 128-bit load & store, Jiajie Chen, 2023/09/02