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[PULL 28/39] accel/tcg: Merge cpu_transaction_failed into io_failed
From: |
Richard Henderson |
Subject: |
[PULL 28/39] accel/tcg: Merge cpu_transaction_failed into io_failed |
Date: |
Fri, 15 Sep 2023 20:30:00 -0700 |
Push computation down into the if statements to the point
the data is used.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 33 +++++++++++++--------------------
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index fd1b07c5a3..f3635afb36 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1350,23 +1350,6 @@ static inline void cpu_unaligned_access(CPUState *cpu,
vaddr addr,
mmu_idx, retaddr);
}
-static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response,
- uintptr_t retaddr)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cpu->ignore_memory_transaction_failures &&
- cc->tcg_ops->do_transaction_failed) {
- cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size,
- access_type, mmu_idx, attrs,
- response, retaddr);
- }
-}
-
static MemoryRegionSection *
io_prepare(hwaddr *out_offset, CPUArchState *env, hwaddr xlat,
MemTxAttrs attrs, vaddr addr, uintptr_t retaddr)
@@ -1390,9 +1373,19 @@ static void io_failed(CPUArchState *env, CPUTLBEntryFull
*full, vaddr addr,
unsigned size, MMUAccessType access_type, int mmu_idx,
MemTxResult response, uintptr_t retaddr)
{
- hwaddr physaddr = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
- cpu_transaction_failed(env_cpu(env), physaddr, addr, size, access_type,
- mmu_idx, full->attrs, response, retaddr);
+ CPUState *cpu = env_cpu(env);
+
+ if (!cpu->ignore_memory_transaction_failures) {
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->tcg_ops->do_transaction_failed) {
+ hwaddr physaddr = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
+
+ cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size,
+ access_type, mmu_idx,
+ full->attrs, response, retaddr);
+ }
+ }
}
static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
--
2.34.1
- [PULL 14/39] tcg/loongarch64: Lower vector min max ops, (continued)
- [PULL 14/39] tcg/loongarch64: Lower vector min max ops, Richard Henderson, 2023/09/15
- [PULL 17/39] tcg/loongarch64: Lower bitsel_vec to vbitsel, Richard Henderson, 2023/09/15
- [PULL 19/39] tcg/loongarch64: Lower rotv_vec ops to LSX, Richard Henderson, 2023/09/15
- [PULL 20/39] tcg/loongarch64: Lower rotli_vec to vrotri, Richard Henderson, 2023/09/15
- [PULL 21/39] tcg/loongarch64: Implement 128-bit load & store, Richard Henderson, 2023/09/15
- [PULL 22/39] tcg: Add gvec compare with immediate and scalar operand, Richard Henderson, 2023/09/15
- [PULL 23/39] target/arm: Use tcg_gen_gvec_cmpi for compare vs 0, Richard Henderson, 2023/09/15
- [PULL 24/39] accel/tcg: Simplify tlb_plugin_lookup, Richard Henderson, 2023/09/15
- [PULL 25/39] accel/tcg: Split out io_prepare and io_failed, Richard Henderson, 2023/09/15
- [PULL 27/39] plugin: Simplify struct qemu_plugin_hwaddr, Richard Henderson, 2023/09/15
- [PULL 28/39] accel/tcg: Merge cpu_transaction_failed into io_failed,
Richard Henderson <=
- [PULL 26/39] accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed, Richard Henderson, 2023/09/15
- [PULL 29/39] accel/tcg: Replace direct use of io_readx/io_writex in do_{ld, st}_1, Richard Henderson, 2023/09/15
- [PULL 31/39] accel/tcg: Merge io_writex into do_st_mmio_leN, Richard Henderson, 2023/09/15
- [PULL 30/39] accel/tcg: Merge io_readx into do_ld_mmio_beN, Richard Henderson, 2023/09/15
- [PULL 33/39] accel/tcg: Introduce do_st16_mmio_leN, Richard Henderson, 2023/09/15
- [PULL 32/39] accel/tcg: Introduce do_ld16_mmio_beN, Richard Henderson, 2023/09/15
- [PULL 34/39] fpu: Add conversions between bfloat16 and [u]int8, Richard Henderson, 2023/09/15
- [PULL 35/39] fpu: Handle m68k extended precision denormals properly, Richard Henderson, 2023/09/15
- [PULL 37/39] util/cpuinfo-aarch64: Add CPUINFO_BTI, Richard Henderson, 2023/09/15
- [PULL 38/39] tcg/aarch64: Emit BTI insns at jump landing pads, Richard Henderson, 2023/09/15