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[PULL 26/39] accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed
From: |
Richard Henderson |
Subject: |
[PULL 26/39] accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed |
Date: |
Fri, 15 Sep 2023 20:29:58 -0700 |
Since the introduction of CPUTLBEntryFull, we can recover
the full cpu address space physical address without having
to examine the MemoryRegionSection.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index ae4ad591fe..a46be6a120 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1388,13 +1388,9 @@ io_prepare(hwaddr *out_offset, CPUArchState *env, hwaddr
xlat,
static void io_failed(CPUArchState *env, CPUTLBEntryFull *full, vaddr addr,
unsigned size, MMUAccessType access_type, int mmu_idx,
- MemTxResult response, uintptr_t retaddr,
- MemoryRegionSection *section, hwaddr mr_offset)
+ MemTxResult response, uintptr_t retaddr)
{
- hwaddr physaddr = (mr_offset +
- section->offset_within_address_space -
- section->offset_within_region);
-
+ hwaddr physaddr = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
cpu_transaction_failed(env_cpu(env), physaddr, addr, size, access_type,
mmu_idx, full->attrs, response, retaddr);
}
@@ -1420,7 +1416,7 @@ static uint64_t io_readx(CPUArchState *env,
CPUTLBEntryFull *full,
if (r != MEMTX_OK) {
io_failed(env, full, addr, memop_size(op), access_type, mmu_idx,
- r, retaddr, section, mr_offset);
+ r, retaddr);
}
return val;
}
@@ -1445,7 +1441,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull
*full,
if (r != MEMTX_OK) {
io_failed(env, full, addr, memop_size(op), MMU_DATA_STORE, mmu_idx,
- r, retaddr, section, mr_offset);
+ r, retaddr);
}
}
--
2.34.1
- [PULL 17/39] tcg/loongarch64: Lower bitsel_vec to vbitsel, (continued)
- [PULL 17/39] tcg/loongarch64: Lower bitsel_vec to vbitsel, Richard Henderson, 2023/09/15
- [PULL 19/39] tcg/loongarch64: Lower rotv_vec ops to LSX, Richard Henderson, 2023/09/15
- [PULL 20/39] tcg/loongarch64: Lower rotli_vec to vrotri, Richard Henderson, 2023/09/15
- [PULL 21/39] tcg/loongarch64: Implement 128-bit load & store, Richard Henderson, 2023/09/15
- [PULL 22/39] tcg: Add gvec compare with immediate and scalar operand, Richard Henderson, 2023/09/15
- [PULL 23/39] target/arm: Use tcg_gen_gvec_cmpi for compare vs 0, Richard Henderson, 2023/09/15
- [PULL 24/39] accel/tcg: Simplify tlb_plugin_lookup, Richard Henderson, 2023/09/15
- [PULL 25/39] accel/tcg: Split out io_prepare and io_failed, Richard Henderson, 2023/09/15
- [PULL 27/39] plugin: Simplify struct qemu_plugin_hwaddr, Richard Henderson, 2023/09/15
- [PULL 28/39] accel/tcg: Merge cpu_transaction_failed into io_failed, Richard Henderson, 2023/09/15
- [PULL 26/39] accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed,
Richard Henderson <=
- [PULL 29/39] accel/tcg: Replace direct use of io_readx/io_writex in do_{ld, st}_1, Richard Henderson, 2023/09/15
- [PULL 31/39] accel/tcg: Merge io_writex into do_st_mmio_leN, Richard Henderson, 2023/09/15
- [PULL 30/39] accel/tcg: Merge io_readx into do_ld_mmio_beN, Richard Henderson, 2023/09/15
- [PULL 33/39] accel/tcg: Introduce do_st16_mmio_leN, Richard Henderson, 2023/09/15
- [PULL 32/39] accel/tcg: Introduce do_ld16_mmio_beN, Richard Henderson, 2023/09/15
- [PULL 34/39] fpu: Add conversions between bfloat16 and [u]int8, Richard Henderson, 2023/09/15
- [PULL 35/39] fpu: Handle m68k extended precision denormals properly, Richard Henderson, 2023/09/15
- [PULL 37/39] util/cpuinfo-aarch64: Add CPUINFO_BTI, Richard Henderson, 2023/09/15
- [PULL 38/39] tcg/aarch64: Emit BTI insns at jump landing pads, Richard Henderson, 2023/09/15
- [PULL 39/39] tcg: Map code_gen_buffer with PROT_BTI, Richard Henderson, 2023/09/15