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[PULL 19/39] tcg/loongarch64: Lower rotv_vec ops to LSX
From: |
Richard Henderson |
Subject: |
[PULL 19/39] tcg/loongarch64: Lower rotv_vec ops to LSX |
Date: |
Fri, 15 Sep 2023 20:29:51 -0700 |
From: Jiajie Chen <c@jia.je>
Lower the following ops:
- rotrv_vec
- rotlv_vec
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230908022302.180442-15-c@jia.je>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 14 ++++++++++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index d7b806e252..d5c69bc192 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -191,7 +191,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
-#define TCG_TARGET_HAS_rotv_vec 0
+#define TCG_TARGET_HAS_rotv_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index c21c917083..8f448823b0 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1743,6 +1743,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const LoongArchInsn sari_vec_insn[4] = {
OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D
};
+ static const LoongArchInsn rotrv_vec_insn[4] = {
+ OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D
+ };
a0 = args[0];
a1 = args[1];
@@ -1890,6 +1893,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sari_vec:
tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2));
break;
+ case INDEX_op_rotrv_vec:
+ tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_rotlv_vec:
+ /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */
+ tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], temp_vec, a2));
+ tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1,
+ temp_vec));
+ break;
case INDEX_op_bitsel_vec:
/* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
@@ -2119,6 +2131,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_rotrv_vec:
+ case INDEX_op_rotlv_vec:
return C_O1_I2(w, w, w);
case INDEX_op_not_vec:
--
2.34.1
- [PULL 11/39] tcg/loongarch64: Lower vector bitwise operations, (continued)
- [PULL 11/39] tcg/loongarch64: Lower vector bitwise operations, Richard Henderson, 2023/09/15
- [PULL 09/39] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt, Richard Henderson, 2023/09/15
- [PULL 12/39] tcg/loongarch64: Lower neg_vec to vneg, Richard Henderson, 2023/09/15
- [PULL 13/39] tcg/loongarch64: Lower mul_vec to vmul, Richard Henderson, 2023/09/15
- [PULL 15/39] tcg/loongarch64: Lower vector saturated ops, Richard Henderson, 2023/09/15
- [PULL 16/39] tcg/loongarch64: Lower vector shift vector ops, Richard Henderson, 2023/09/15
- [PULL 18/39] tcg/loongarch64: Lower vector shift integer ops, Richard Henderson, 2023/09/15
- [PULL 06/39] tcg/loongarch64: Import LSX instructions, Richard Henderson, 2023/09/15
- [PULL 14/39] tcg/loongarch64: Lower vector min max ops, Richard Henderson, 2023/09/15
- [PULL 17/39] tcg/loongarch64: Lower bitsel_vec to vbitsel, Richard Henderson, 2023/09/15
- [PULL 19/39] tcg/loongarch64: Lower rotv_vec ops to LSX,
Richard Henderson <=
- [PULL 20/39] tcg/loongarch64: Lower rotli_vec to vrotri, Richard Henderson, 2023/09/15
- [PULL 21/39] tcg/loongarch64: Implement 128-bit load & store, Richard Henderson, 2023/09/15
- [PULL 22/39] tcg: Add gvec compare with immediate and scalar operand, Richard Henderson, 2023/09/15
- [PULL 23/39] target/arm: Use tcg_gen_gvec_cmpi for compare vs 0, Richard Henderson, 2023/09/15
- [PULL 24/39] accel/tcg: Simplify tlb_plugin_lookup, Richard Henderson, 2023/09/15
- [PULL 25/39] accel/tcg: Split out io_prepare and io_failed, Richard Henderson, 2023/09/15
- [PULL 27/39] plugin: Simplify struct qemu_plugin_hwaddr, Richard Henderson, 2023/09/15
- [PULL 28/39] accel/tcg: Merge cpu_transaction_failed into io_failed, Richard Henderson, 2023/09/15
- [PULL 26/39] accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed, Richard Henderson, 2023/09/15
- [PULL 29/39] accel/tcg: Replace direct use of io_readx/io_writex in do_{ld, st}_1, Richard Henderson, 2023/09/15