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[PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs
From: |
Jonathan Cameron |
Subject: |
[PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs |
Date: |
Mon, 25 Sep 2023 17:11:13 +0100 |
Add initial documentation for the MCTP over I2C management device. At
current time this can only be used with the Aspeed I2C controller which
is only available in aspeed SoCs, though can be added to other
emulated boards.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
docs/system/devices/cxl.rst | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 6ab5f72473..dfe5577599 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -406,6 +406,33 @@ OS management of CXL memory devices as described here.
* CONFIG_CXL_PORT
* CONFIG_CXL_REGION
+
+CCI access via MCTP over I2C
+----------------------------
+
+In order to make use of this device, an I2C controller that supports MCTP
+is required. The aspeed-i2c controller is an example of such a controller.
+
+Both CXL switches and CXL Type 3 devices support configuration via
+MCTP access to Component Command Interfaces (CCIs) on the devices.
+
+Example configuration:
+
+ -device
cxl-upstream,port=33,bus=root_port0,id=us0,multifunction=on,addr=0.0,sn=12345678
\
+ -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \
+ -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \
+ -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \
+ -device
cxl-type3,bus=swport0,persistent-memdev=cxl-mem1,id=cxl-pmem0,lsa=cxl-lsa1,sn=3
\
+ -device
cxl-type3,bus=swport1,persistent-memdev=cxl-mem2,id=cxl-pmem1,lsa=cxl-lsa2,sn=4
\
+ -device
cxl-type3,bus=swport2,persistent-memdev=cxl-mem3,id=cxl-pmem2,lsa=cxl-lsa3,sn=5
\
+ -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=4,target=us0 \
+ -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=5,target=cxl-pmem0 \
+ -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=6,target=cxl-pmem1 \
+ -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=7,target=cxl-pmem2
+
+Guest OS communication with the MCTP CCI can then be established using standard
+MCTP configuration tools.
+
References
----------
--
2.39.2
- [PATCH 00/19] QEMU: CXL mailbox rework and features, Jonathan Cameron, 2023/09/25
- [PATCH 01/19] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant, Jonathan Cameron, 2023/09/25
- [PATCH 02/19] hw/cxl/mbox: Split mailbox command payload into separate input and output, Jonathan Cameron, 2023/09/25
- [PATCH 03/19] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState, Jonathan Cameron, 2023/09/25
- [PATCH 04/19] hw/cxl/mbox: Generalize the CCI command processing, Jonathan Cameron, 2023/09/25
- [PATCH 05/19] hw/pci-bridge/cxl_upstream: Move defintion of device to header., Jonathan Cameron, 2023/09/25
- [PATCH 06/19] hw/cxl/i2c_mctp_cxl: Initial device emulation, Jonathan Cameron, 2023/09/25
- [PATCH 07/19] hw/cxl/mbox: Add Information and Status / Identify command, Jonathan Cameron, 2023/09/25
- [PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs,
Jonathan Cameron <=
- [PATCH 09/19] hw/cxl/mbox: Add Physical Switch Identify command., Jonathan Cameron, 2023/09/25
- [PATCH 10/19] hw/cxl: Add a switch mailbox CCI function, Jonathan Cameron, 2023/09/25
- [PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and link speed, Jonathan Cameron, 2023/09/25
- [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval, Jonathan Cameron, 2023/09/25
- [PATCH 13/19] hw/cxl/mbox: Add Get Background Operation Status Command, Jonathan Cameron, 2023/09/25
- [PATCH 14/19] hw/cxl/mbox: Add support for background operations, Jonathan Cameron, 2023/09/25
- [PATCH 15/19] hw/cxl/mbox: Wire up interrupts for background completion, Jonathan Cameron, 2023/09/25
- [PATCH 16/19] hw/cxl: Add support for device sanitation, Jonathan Cameron, 2023/09/25
- [PATCH 17/19] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions, Jonathan Cameron, 2023/09/25