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[PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and l
From: |
Jonathan Cameron |
Subject: |
[PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and link speed |
Date: |
Mon, 25 Sep 2023 17:11:16 +0100 |
Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/pci-bridge/cxl_downstream.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
index 8d99e1e96d..405a133eef 100644
--- a/hw/pci-bridge/cxl_downstream.c
+++ b/hw/pci-bridge/cxl_downstream.c
@@ -210,6 +210,19 @@ static void cxl_dsp_exitfn(PCIDevice *d)
pci_bridge_exitfn(d);
}
+static void cxl_dsp_instance_post_init(Object *obj)
+{
+ PCIESlot *s = PCIE_SLOT(obj);
+
+ if (!s->speed) {
+ s->speed = QEMU_PCI_EXP_LNK_2_5GT;
+ }
+
+ if (!s->width) {
+ s->width = QEMU_PCI_EXP_LNK_X1;
+ }
+}
+
static void cxl_dsp_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -230,6 +243,7 @@ static const TypeInfo cxl_dsp_info = {
.name = TYPE_CXL_DSP,
.instance_size = sizeof(CXLDownstreamPort),
.parent = TYPE_PCIE_SLOT,
+ .instance_post_init = cxl_dsp_instance_post_init,
.class_init = cxl_dsp_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_PCIE_DEVICE },
--
2.39.2
- [PATCH 01/19] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant, (continued)
- [PATCH 01/19] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant, Jonathan Cameron, 2023/09/25
- [PATCH 02/19] hw/cxl/mbox: Split mailbox command payload into separate input and output, Jonathan Cameron, 2023/09/25
- [PATCH 03/19] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState, Jonathan Cameron, 2023/09/25
- [PATCH 04/19] hw/cxl/mbox: Generalize the CCI command processing, Jonathan Cameron, 2023/09/25
- [PATCH 05/19] hw/pci-bridge/cxl_upstream: Move defintion of device to header., Jonathan Cameron, 2023/09/25
- [PATCH 06/19] hw/cxl/i2c_mctp_cxl: Initial device emulation, Jonathan Cameron, 2023/09/25
- [PATCH 07/19] hw/cxl/mbox: Add Information and Status / Identify command, Jonathan Cameron, 2023/09/25
- [PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs, Jonathan Cameron, 2023/09/25
- [PATCH 09/19] hw/cxl/mbox: Add Physical Switch Identify command., Jonathan Cameron, 2023/09/25
- [PATCH 10/19] hw/cxl: Add a switch mailbox CCI function, Jonathan Cameron, 2023/09/25
- [PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and link speed,
Jonathan Cameron <=
- [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval, Jonathan Cameron, 2023/09/25
- [PATCH 13/19] hw/cxl/mbox: Add Get Background Operation Status Command, Jonathan Cameron, 2023/09/25
- [PATCH 14/19] hw/cxl/mbox: Add support for background operations, Jonathan Cameron, 2023/09/25
- [PATCH 15/19] hw/cxl/mbox: Wire up interrupts for background completion, Jonathan Cameron, 2023/09/25
- [PATCH 16/19] hw/cxl: Add support for device sanitation, Jonathan Cameron, 2023/09/25
- [PATCH 17/19] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions, Jonathan Cameron, 2023/09/25
- [PATCH 18/19] hw/cxl: Add dummy security state get, Jonathan Cameron, 2023/09/25
- [PATCH 19/19] hw/cxl: Add tunneled command support to mailbox for switch cci/mctp., Jonathan Cameron, 2023/09/25
- Re: [PATCH 00/19] QEMU: CXL mailbox rework and features, Jonathan Cameron, 2023/09/25