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[PATCH 15/19] hw/cxl/mbox: Wire up interrupts for background completion
From: |
Jonathan Cameron |
Subject: |
[PATCH 15/19] hw/cxl/mbox: Wire up interrupts for background completion |
Date: |
Mon, 25 Sep 2023 17:11:20 +0100 |
From: Davidlohr Bueso <dave@stgolabs.net>
Notify when the background operation is done. Note that for now background
commands are only supported on the main Type 3 mailbox.
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
include/hw/cxl/cxl_device.h | 1 +
hw/cxl/cxl-device-utils.c | 10 +++++++++-
hw/cxl/cxl-mailbox-utils.c | 31 ++++++++++++++-----------------
3 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index a99a7e6274..b7fa57fd14 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -193,6 +193,7 @@ typedef struct cxl_device_state {
struct {
MemoryRegion mailbox;
uint16_t payload_size;
+ uint8_t mbox_msi_n;
union {
uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH];
uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2];
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index 88f0256c79..41763688ce 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -345,10 +345,18 @@ static void device_reg_init_common(CXLDeviceState
*cxl_dstate)
static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
{
- /* 2048 payload size, with no interrupt */
+ const uint8_t msi_n = 9;
+
+ /* 2048 payload size */
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT);
cxl_dstate->payload_size = CXL_MAILBOX_MAX_PAYLOAD_SIZE;
+ /* irq support */
+ ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
+ BG_INT_CAP, 1);
+ ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
+ MSI_N, msi_n);
+ cxl_dstate->mbox_msi_n = msi_n;
}
static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { }
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 63acbc1214..3db86b4da7 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -8,6 +8,8 @@
*/
#include "qemu/osdep.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/msix.h"
#include "hw/cxl/cxl.h"
#include "hw/cxl/cxl_events.h"
#include "hw/pci/pci.h"
@@ -1092,28 +1094,16 @@ int cxl_process_cci_message(CXLCCI *cci, uint8_t set,
uint8_t cmd,
static void bg_timercb(void *opaque)
{
CXLCCI *cci = opaque;
- CXLDeviceState *cxl_dstate = &CXL_TYPE3(cci->d)->cxl_dstate;
- uint64_t bg_status_reg = 0;
uint64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
uint64_t total_time = cci->bg.starttime + cci->bg.runtime;
assert(cci->bg.runtime > 0);
- bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
- OP, cci->bg.opcode);
if (now >= total_time) { /* we are done */
- uint64_t status_reg;
uint16_t ret = CXL_MBOX_SUCCESS;
cci->bg.complete_pct = 100;
- /* Clear bg */
- status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, BG_OP, 0);
- cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
-
- bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
- RET_CODE, ret);
-
- /* TODO add ad-hoc cmd succesful completion handling */
+ cci->bg.ret_code = ret;
qemu_log("Background command %04xh finished: %s\n",
cci->bg.opcode,
@@ -1124,14 +1114,21 @@ static void bg_timercb(void *opaque)
timer_mod(cci->bg.timer, now + CXL_MBOX_BG_UPDATE_FREQ);
}
- bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
- PERCENTAGE_COMP, cci->bg.complete_pct);
- cxl_dstate->mbox_reg_state64[R_CXL_DEV_BG_CMD_STS] = bg_status_reg;
-
if (cci->bg.complete_pct == 100) {
+ /* TODO: generalize to switch CCI */
+ CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
+ CXLDeviceState *cxl_dstate = &ct3d->cxl_dstate;
+ PCIDevice *pdev = PCI_DEVICE(cci->d);
+
cci->bg.starttime = 0;
/* registers are updated, allow new bg-capable cmds */
cci->bg.runtime = 0;
+
+ if (msix_enabled(pdev)) {
+ msix_notify(pdev, cxl_dstate->mbox_msi_n);
+ } else if (msi_enabled(pdev)) {
+ msi_notify(pdev, cxl_dstate->mbox_msi_n);
+ }
}
}
--
2.39.2
- [PATCH 06/19] hw/cxl/i2c_mctp_cxl: Initial device emulation, (continued)
- [PATCH 06/19] hw/cxl/i2c_mctp_cxl: Initial device emulation, Jonathan Cameron, 2023/09/25
- [PATCH 07/19] hw/cxl/mbox: Add Information and Status / Identify command, Jonathan Cameron, 2023/09/25
- [PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs, Jonathan Cameron, 2023/09/25
- [PATCH 09/19] hw/cxl/mbox: Add Physical Switch Identify command., Jonathan Cameron, 2023/09/25
- [PATCH 10/19] hw/cxl: Add a switch mailbox CCI function, Jonathan Cameron, 2023/09/25
- [PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and link speed, Jonathan Cameron, 2023/09/25
- [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval, Jonathan Cameron, 2023/09/25
- [PATCH 13/19] hw/cxl/mbox: Add Get Background Operation Status Command, Jonathan Cameron, 2023/09/25
- [PATCH 14/19] hw/cxl/mbox: Add support for background operations, Jonathan Cameron, 2023/09/25
- [PATCH 15/19] hw/cxl/mbox: Wire up interrupts for background completion,
Jonathan Cameron <=
- [PATCH 16/19] hw/cxl: Add support for device sanitation, Jonathan Cameron, 2023/09/25
- [PATCH 17/19] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions, Jonathan Cameron, 2023/09/25
- [PATCH 18/19] hw/cxl: Add dummy security state get, Jonathan Cameron, 2023/09/25
- [PATCH 19/19] hw/cxl: Add tunneled command support to mailbox for switch cci/mctp., Jonathan Cameron, 2023/09/25
- Re: [PATCH 00/19] QEMU: CXL mailbox rework and features, Jonathan Cameron, 2023/09/25
- Re: [PATCH 00/19] QEMU: CXL mailbox rework and features, Gregory Price, 2023/09/28