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Re: [PATCH v5 39/60] target/riscv: vector floating-point classify instru
From: |
Richard Henderson |
Subject: |
Re: [PATCH v5 39/60] target/riscv: vector floating-point classify instructions |
Date: |
Sat, 14 Mar 2020 02:10:55 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Floating-Point Classify Instruction */
> +static uint16_t fclass_f16(uint16_t frs1, float_status *s)
> +{
> + float16 f = frs1;
> + bool sign = float16_is_neg(f);
> +
> + if (float16_is_infinity(f)) {
> + return sign ? 1 << 0 : 1 << 7;
> + } else if (float16_is_zero(f)) {
> + return sign ? 1 << 3 : 1 << 4;
> + } else if (float16_is_zero_or_denormal(f)) {
> + return sign ? 1 << 2 : 1 << 5;
> + } else if (float16_is_any_nan(f)) {
> + float_status s = { }; /* for snan_bit_is_one */
> + return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> + } else {
> + return sign ? 1 << 1 : 1 << 6;
> + }
> +}
> +static uint32_t fclass_s(uint32_t frs1, float_status *s)
> +{
> + float32 f = frs1;
> + bool sign = float32_is_neg(f);
> +
> + if (float32_is_infinity(f)) {
> + return sign ? 1 << 0 : 1 << 7;
> + } else if (float32_is_zero(f)) {
> + return sign ? 1 << 3 : 1 << 4;
> + } else if (float32_is_zero_or_denormal(f)) {
> + return sign ? 1 << 2 : 1 << 5;
> + } else if (float32_is_any_nan(f)) {
> + float_status s = { }; /* for snan_bit_is_one */
> + return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> + } else {
> + return sign ? 1 << 1 : 1 << 6;
> + }
> +}
> +static uint64_t fclass_d(uint64_t frs1, float_status *s)
> +{
> + float64 f = frs1;
> + bool sign = float64_is_neg(f);
> +
> + if (float64_is_infinity(f)) {
> + return sign ? 1 << 0 : 1 << 7;
> + } else if (float64_is_zero(f)) {
> + return sign ? 1 << 3 : 1 << 4;
> + } else if (float64_is_zero_or_denormal(f)) {
> + return sign ? 1 << 2 : 1 << 5;
> + } else if (float64_is_any_nan(f)) {
> + float_status s = { }; /* for snan_bit_is_one */
> + return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> + } else {
> + return sign ? 1 << 1 : 1 << 6;
> + }
> +}
These need to be moved out of fpu_helper.c so they can be shared.
r~
- Re: [PATCH v5 34/60] target/riscv: vector widening floating-point fused multiply-add instructions, (continued)
- [PATCH v5 35/60] target/riscv: vector floating-point square-root instruction, LIU Zhiwei, 2020/03/12
- [PATCH v5 36/60] target/riscv: vector floating-point min/max instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 37/60] target/riscv: vector floating-point sign-injection instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 38/60] target/riscv: vector floating-point compare instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 39/60] target/riscv: vector floating-point classify instructions, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 39/60] target/riscv: vector floating-point classify instructions,
Richard Henderson <=
- [PATCH v5 40/60] target/riscv: vector floating-point merge instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 41/60] target/riscv: vector floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 42/60] target/riscv: widening floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12