[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5
From: |
Palmer Dabbelt |
Subject: |
[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5 |
Date: |
Mon, 16 Mar 2020 21:05:41 -0700 |
The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request'
into staging (2020-03-16 14:55:59 +0000)
are available in the Git repository at:
address@hidden:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf5
for you to fetch changes up to c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264:
target/riscv: Fix VS mode interrupts forwarding. (2020-03-16 17:03:51 -0700)
----------------------------------------------------------------
RISC-V Patches for the 5.0 Soft Freeze, Part 5
This tag contains the last of the patches I'd like to target for the 5.0 soft
freeze. At this point we're mostly collecting fixes, but there are a few new
features. The changes include:
* An OpenSBI update, including the various bits necessary to put CI together
and an image for the 32-bit sifive_u board.
* A fix that disallows TSR when outside of machine mode.
* A fix for VS-mode interrupt forwarding.
----------------------------------------------------------------
Alistair Francis (1):
target/riscv: Correctly implement TSR trap
Bin Meng (4):
roms: opensbi: Upgrade from v0.5 to v0.6
roms: opensbi: Add 32-bit firmware image for sifive_u machine
riscv: sifive_u: Update BIOS_FILENAME for 32-bit
gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries
Rajnesh Kanwal (1):
target/riscv: Fix VS mode interrupts forwarding.
.gitlab-ci-opensbi.yml | 63 +++++++++++++++++++++++++++
.gitlab-ci.d/opensbi/Dockerfile | 33 ++++++++++++++
.gitlab-ci.yml | 1 +
Makefile | 2 +-
hw/riscv/sifive_u.c | 6 ++-
pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 0 -> 49472 bytes
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 40984 -> 41280 bytes
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 49160 -> 53760 bytes
pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 45064 -> 49664 bytes
roms/Makefile | 7 +++
roms/opensbi | 2 +-
target/riscv/cpu_helper.c | 9 +++-
target/riscv/op_helper.c | 2 +-
13 files changed, 120 insertions(+), 5 deletions(-)
create mode 100644 .gitlab-ci-opensbi.yml
create mode 100644 .gitlab-ci.d/opensbi/Dockerfile
create mode 100644 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5,
Palmer Dabbelt <=
- [PULL 1/6] target/riscv: Correctly implement TSR trap, Palmer Dabbelt, 2020/03/17
- [PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit, Palmer Dabbelt, 2020/03/17
- [PULL 6/6] target/riscv: Fix VS mode interrupts forwarding., Palmer Dabbelt, 2020/03/17
- [PULL 5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries, Palmer Dabbelt, 2020/03/17
- [PULL 3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine, Palmer Dabbelt, 2020/03/17
- [PULL 2/6] roms: opensbi: Upgrade from v0.5 to v0.6, Palmer Dabbelt, 2020/03/17
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5, Peter Maydell, 2020/03/17