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[PULL 6/6] target/riscv: Fix VS mode interrupts forwarding.
From: |
Palmer Dabbelt |
Subject: |
[PULL 6/6] target/riscv: Fix VS mode interrupts forwarding. |
Date: |
Mon, 16 Mar 2020 21:05:47 -0700 |
From: Rajnesh Kanwal <address@hidden>
Currently riscv_cpu_local_irq_pending is used to find out pending
interrupt and VS mode interrupts are being shifted to represent
S mode interrupts in this function. So when the cause returned by
this function is passed to riscv_cpu_do_interrupt to actually
forward the interrupt, the VS mode forwarding check does not work
as intended and interrupt is actually forwarded to hypervisor. This
patch fixes this issue.
Signed-off-by: Rajnesh Kanwal <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5ea5d133aa..d3ba9efb02 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
target_ulong pending = env->mip & env->mie &
~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
target_ulong vspending = (env->mip & env->mie &
- (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
+ (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
target_ulong mie = env->priv < PRV_M ||
(env->priv == PRV_M && mstatus_mie);
@@ -907,6 +907,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
+ /*
+ * See if we need to adjust cause. Yes if its VS mode interrupt
+ * no if hypervisor has delegated one of hs mode's interrupt
+ */
+ if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
+ cause == IRQ_VS_EXT)
+ cause = cause - 1;
/* Trap to VS mode */
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
--
2.25.1.481.gfbce0eb801-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5, Palmer Dabbelt, 2020/03/17
- [PULL 1/6] target/riscv: Correctly implement TSR trap, Palmer Dabbelt, 2020/03/17
- [PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit, Palmer Dabbelt, 2020/03/17
- [PULL 6/6] target/riscv: Fix VS mode interrupts forwarding.,
Palmer Dabbelt <=
- [PULL 5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries, Palmer Dabbelt, 2020/03/17
- [PULL 3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine, Palmer Dabbelt, 2020/03/17
- [PULL 2/6] roms: opensbi: Upgrade from v0.5 to v0.6, Palmer Dabbelt, 2020/03/17
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5, Peter Maydell, 2020/03/17