[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 1/6] target/riscv: Correctly implement TSR trap
From: |
Palmer Dabbelt |
Subject: |
[PULL 1/6] target/riscv: Correctly implement TSR trap |
Date: |
Mon, 16 Mar 2020 21:05:42 -0700 |
From: Alistair Francis <address@hidden>
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.
This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 8736f689c2..c6412f680c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -85,7 +85,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong
cpu_pc_deb)
}
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TSR)) {
+ get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
--
2.25.1.481.gfbce0eb801-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5, Palmer Dabbelt, 2020/03/17
- [PULL 1/6] target/riscv: Correctly implement TSR trap,
Palmer Dabbelt <=
- [PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit, Palmer Dabbelt, 2020/03/17
- [PULL 6/6] target/riscv: Fix VS mode interrupts forwarding., Palmer Dabbelt, 2020/03/17
- [PULL 5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries, Palmer Dabbelt, 2020/03/17
- [PULL 3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine, Palmer Dabbelt, 2020/03/17
- [PULL 2/6] roms: opensbi: Upgrade from v0.5 to v0.6, Palmer Dabbelt, 2020/03/17
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5, Peter Maydell, 2020/03/17