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[RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from us
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From: |
frank . chang |
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Subject: |
[RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec |
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Date: |
Fri, 10 Jul 2020 18:48:19 +0800 |
From: Frank Chang <frank.chang@sifive.com>
vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
shift immediate value to be within the range: [0.. SEW bits].
Otherwise, it will hit the assertion:
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
However, RVV spec does not have such constraint, therefore we have to
use helper functions instead.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index c0b7375927..70d31a5525 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1427,9 +1427,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
+GEN_OPIVI_TRANS(vsll_vi, 1, vsll_vx, opivx_check)
+GEN_OPIVI_TRANS(vsrl_vi, 1, vsrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vsra_vi, 1, vsra_vx, opivx_check)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.17.1
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, (continued)
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec,
frank . chang <=
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/14
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/10
[RFC 13/65] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/10