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Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns fro
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From: |
Richard Henderson |
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Subject: |
Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec |
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Date: |
Tue, 14 Jul 2020 06:21:53 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/13/20 7:59 PM, Frank Chang wrote:
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from a
> *register value*.
> The *immediate* is treated as an *unsigned shift amount*, with a *maximum
> shift
> amount of 31*.
Which, I hope you will agree is underspecified, and should be reported as a bug
in the manual.
> Looks like the shift amount in the immediate value is not relevant with SEW
> setting.
How can it not be? It is when the value comes from a register...
> If so, is it better to just use do_opivi_gvec() and implement the logic by our
> own rather than using gvec IR?
No, it is not. What is the logic you would apply on your own? There should be
a right answer.
If the answer is that out-of-range shift produces zero, which some
architectures use, then you can look at the immediate value, see that you must
supply zero, and then fill the vector with zeros from translate. You need not
call a helper to perform N shifts when you know the result a-priori.
If the answer is that shift values are truncated, which riscv uses *everywhere
else*, then you should truncate the immediate value during translate.
r~
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, (continued)
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, frank . chang, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec,
Richard Henderson <=
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/14
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/10
[RFC 13/65] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/10
[RFC 15/65] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/10
[RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/10
[RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation, frank . chang, 2020/07/10