[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register
From: |
frank . chang |
Subject: |
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register |
Date: |
Fri, 10 Jul 2020 18:48:23 +0800 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++++++
4 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bdb5d..871c2ddfa1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
env->mcause = 0;
env->pc = env->resetvec;
+ env->vlenb = cpu->cfg.vlen >> 3;
#endif
cs->exception_index = EXCP_NONE;
env->load_res = -1;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c02690ed0d..81c85bf4c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,6 +111,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ target_ulong vlenb;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 79ae0accbc..62789e3720 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -63,6 +63,7 @@
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 77d371f385..6b05c631f4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -197,6 +197,12 @@ static int read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
return 0;
}
+static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vlenb;
+ return 0;
+}
+
static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vl;
@@ -1301,6 +1307,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VCSR] = { vs, read_vcsr, write_vcsr },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
+ [CSR_VLENB] = { vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { ctr, read_instret },
[CSR_INSTRET] = { ctr, read_instret },
--
2.17.1
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, (continued)
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, frank . chang, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/14
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register,
frank . chang <=
[RFC 13/65] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/10
[RFC 15/65] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/10
[RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/10
[RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation, frank . chang, 2020/07/10
[RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/10
[RFC 28/65] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/10
[RFC 32/65] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/10