Re: urgent help on Makefile

[Paul D. Smith]

%% Yin Lei <address@hidden> writes:

  yl> Based on your recommendation, I still have some questions:
  yl> If I wrote some sub-makefile such as: "proj1.mk, proj2.mk, ..."
  yl> the contents of them are:

  yl> proj1.mk
  yl> --------
  yl> SRC       = foo1.c bar1.c baz1.c
  yl> proj1:    $(SRCS:.c=.o)

  yl> proj2.mk
  yl> --------
  yl> SRC       = foo2.c bar2.c baz2.c
  yl> proj2:    $(SRC:.c=.o)

  yl> ...

  yl> And the main Makefile as:

  yl> MODULE_LIST = proj1 proj2 proj3 ...
  yl> include $(MODULE_LIST:%=%.mk)

  yl> $(MODULE_LIST):
  yl>   <do whatever to build a module>

  yl> what make me confuse is: if there is any confliction because the
  yl> variable name of each "*.mk" are same?

No, not in this case.

It's critically important, when using make, to understand its two-phase
processing model and to understand when variables are expanded
immediately, and when their expansion is deferred until later.

There are some sections of the GNU make manual dealing with this.

In the case of prerequisite lists, like this:

  proj2: $(SRC:.c=.o)

the value of the variable is expanded immediately, as the makefile is
read in.  That means that later on, when you reset the value of SRC and
use it again, it doesn't matter to _this_ rule (proj2) because the value
was already expanded.

-- 
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 Paul D. Smith <address@hidden>          Find some GNU make tips at:
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 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist