Re: urgent help on Makefile

[Yin Lei]

nOn Tue, 8 May 2001, Paul D. Smith wrote:

> In general, you can do _LOTS_ of very funky things with this feature.
>
>   yl> PROJECT_LIST    = proj1 proj2
>
>   yl> include $(PROJECT_LIST:%=%.mk)
>
>   yl> $(PROJECT_LIST):
>   yl>         @echo "making address@hidden"
>   yl>         @echo $($*_ARCH_OBJS)
>
>   yl> The question is, this makefile can't build two targets at
>   yl> once. When I type "make", it only active "proj1". The "proj2" will
>   yl> never be made until I type "make proj2"
>
> That's easy, you just need an "all" rule as the first thing in your
> top-level makefile:
>
>   all: $(PROJECT_LIST)
>
>   $(PROJECT_LIST):
>         @echo ...
>

Hi, Paul:

Above method for making all targets at one time doesn't work, except
by typing "make all"

Following is my new makefile template:

proj1.mk
--------
PROJECT_NAME            = proj1
$(PROJECT_NAME)_ARCH_FILES      := foo.c bar.c baz.c
$(PROJECT_NAME)_ARCH_OBJS       := $($(PROJECT_NAME)_ARCH_FILES:%.c=%.o)

$(PROJECT_NAME): $($(PROJECT_NAME)_ARCH_FILES:%.c=%.o)

$($(PROJECT_NAME)_ARCH_OBJS):
        touch $@

proj2.mk
--------
PROJECT_NAME            = proj2
$(PROJECT_NAME)_ARCH_FILES      := foo2.c bar2.c baz2.c
$(PROJECT_NAME)_ARCH_OBJS       := $($(PROJECT_NAME)_ARCH_FILES:%.c=%.o)

$(PROJECT_NAME): $($(PROJECT_NAME)_ARCH_FILES:%.c=%.o)

$($(PROJECT_NAME)_ARCH_OBJS):
        touch $@

Makefile(top-level)
------------------
PROJECT_LIST    = proj1 proj2

include $(PROJECT_LIST:%=%.mk)

all:    $(PROJECT_LIST)

.PHONY: all

$(PROJECT_LIST):
        @echo "making ...$@"
        @echo $(address@hidden)
        @echo

It's so strange. I think that it isn't caused by expanding, because
the problem still remain even modify the "all" rule as

all: proj1 proj2

Is there anything wrong?

-- 
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Lei Yin, Ph.D
Celestry Design Technologies, Inc
1982A Zanker Road, San Jose, CA 95112
Tel: (408)501-2313(O) | Fax: (408)501-2607
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