Re: [libreplanet-discuss] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation

[Staf Verhaegen]

   Luke Kenneth Casson Leighton schreef op di 24-09-2019 om 12:16 [+0100]:

On Tue, Sep 24, 2019 at 9:55 AM Hagen SANKOWSKI <


hsank@posteo.de
> wrote:


The main difference between AMBI AXI and Wishbone is the streaming
capability. AXI can stream data, just with repetition stages, without
handshake signals. So, it would be easier and more sustainable to
bring-up Wishbone to the next level by standardize a similar streaming
feature. And yes, there are a lot of cores which using AMBA AXI which
had to be partly re-written for Wishbone. But currently, there is no
alternative, or as the German chancellor Merkel likes to say:
"alternativlos". With added streaming feature to Wishbone, we would get
an alternative full-featured SoC Bus and Designers could fix their bad
AMBA AXI bus interfaces..



great: this sounds like a perfect *additional* Research Project which
someone [else] could put in a request for funding.  once it is
available, we can look at converting the code over to use it, and
converting any peripherals to use it.

or, if someone [else] wants to include the Libre RISC-V SoC peripheral
set as a possible suite of examples to convert (which would help
justify a budget of EUR 50,000) they are welcome to do so.

the relevance of the streaming capability is that we need an I2S Audio Bus.

i can help with a write-up: unfortunately i am hitting an _additional_
limit of EUR 250,000 per person for overall projects submitted, so
cannot be the one to submit it.

   Have yo guys looked at the pipeline feature of Wishbone B4 ? What is
   missing there to make streaming possible ?

   greets,

   Staf.

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