[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 28/28] hw/arm/virt-acpi-build: Add SPCR table
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 28/28] hw/arm/virt-acpi-build: Add SPCR table |
Date: |
Mon, 15 Jun 2015 18:24:58 +0100 |
From: Andrew Jones <address@hidden>
Signed-off-by: Andrew Jones <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/virt-acpi-build.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index a9373cc..d5a8b9c 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -84,6 +84,12 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
*uart_memmap,
aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
AML_EXCLUSIVE, uart_irq));
aml_append(dev, aml_name_decl("_CRS", crs));
+
+ /* The _ADR entry is used to link this device to the UART described
+ * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
+ */
+ aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
+
aml_append(scope, dev);
}
@@ -334,6 +340,38 @@ build_rsdp(GArray *rsdp_table, GArray *linker, unsigned
rsdt)
}
static void
+build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ AcpiSerialPortConsoleRedirection *spcr;
+ const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART];
+ int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE;
+
+ spcr = acpi_data_push(table_data, sizeof(*spcr));
+
+ spcr->interface_type = 0x3; /* ARM PL011 UART */
+
+ spcr->base_address.space_id = AML_SYSTEM_MEMORY;
+ spcr->base_address.bit_width = 8;
+ spcr->base_address.bit_offset = 0;
+ spcr->base_address.access_width = 1;
+ spcr->base_address.address = cpu_to_le64(uart_memmap->base);
+
+ spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
+ spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
+
+ spcr->baud = 3; /* Baud Rate: 3 = 9600 */
+ spcr->parity = 0; /* No Parity */
+ spcr->stopbits = 1; /* 1 Stop bit */
+ spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
+ spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
+
+ spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
+ spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
+
+ build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2);
+}
+
+static void
build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
{
AcpiTableMcfg *mcfg;
@@ -514,7 +552,7 @@ void virt_acpi_build(VirtGuestInfo *guest_info,
AcpiBuildTables *tables)
dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, guest_info);
- /* FADT MADT GTDT pointed to by RSDT */
+ /* FADT MADT GTDT SPCR pointed to by RSDT */
acpi_add_table(table_offsets, tables_blob);
build_fadt(tables_blob, tables->linker, dsdt);
@@ -527,6 +565,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_mcfg(tables_blob, tables->linker, guest_info);
+ acpi_add_table(table_offsets, tables_blob);
+ build_spcr(tables_blob, tables->linker, guest_info);
+
/* RSDT is pointed to by RSDP */
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets);
--
1.9.1
- [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 27/28] ACPI: Add definitions for the SPCR table, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 03/28] arm_gic: gic_update should always update all cores, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 28/28] hw/arm/virt-acpi-build: Add SPCR table,
Peter Maydell <=
- [Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address" for cpreg access exceptions, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 25/28] hw/arm/boot: fix rom_reset notifier registration order, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 24/28] arm: helper: rename get_phys_addr_mpu, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 22/28] arm: Implement uniprocessor with MP config, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 23/28] arm: Add has-mpu property, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 19/28] arm: Don't add v7mp registers in MPU systems, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 20/28] arm: helper: Factor out CP regs common to [pv]msa, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 18/28] arm: Do not define TLBTR in PMSA systems, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 16/28] hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 15/28] hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState, Peter Maydell, 2015/06/15