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[Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address"
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address" for cpreg access exceptions |
Date: |
Mon, 15 Jun 2015 18:24:56 +0100 |
The architecture defines that when taking an exception trying to
access a coprocessor register, the "preferred return address" for
the exception is the address of the instruction that caused the
exception. Correct an off-by-4 error which meant we were returning
the address after the instruction for traps which happened because
of a failure of a runtime access-check function on an AArch32
register. (Traps caused by translate-time checkable permissions
failures had the correct address, as did traps on AArch64 registers.)
This fixes https://bugs.launchpad.net/qemu/+bug/1463338
Reported-by: Robert Buhren <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target-arm/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 125b6da..ead08f4 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7175,7 +7175,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t
insn)
break;
}
- gen_set_pc_im(s, s->pc);
+ gen_set_pc_im(s, s->pc - 4);
tmpptr = tcg_const_ptr(ri);
tcg_syn = tcg_const_i32(syndrome);
gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn);
--
1.9.1
- [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 27/28] ACPI: Add definitions for the SPCR table, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 03/28] arm_gic: gic_update should always update all cores, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 28/28] hw/arm/virt-acpi-build: Add SPCR table, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address" for cpreg access exceptions,
Peter Maydell <=
- [Qemu-devel] [PULL 25/28] hw/arm/boot: fix rom_reset notifier registration order, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 24/28] arm: helper: rename get_phys_addr_mpu, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 22/28] arm: Implement uniprocessor with MP config, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 23/28] arm: Add has-mpu property, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 19/28] arm: Don't add v7mp registers in MPU systems, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 20/28] arm: helper: Factor out CP regs common to [pv]msa, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 18/28] arm: Do not define TLBTR in PMSA systems, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 16/28] hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 15/28] hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 12/28] hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO, Peter Maydell, 2015/06/15