[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 12/28] hw/arm/pxa2xx: Mark coprocessor registers as A
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/28] hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO |
Date: |
Mon, 15 Jun 2015 18:24:42 +0100 |
The pxa2xx custom coprocessor registers in cp6 and cp14 do device
accesses, so mark the non-constant regs as ARM_CP_IO so that
icount works correctly and doesn't abort.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
---
hw/arm/pxa2xx.c | 8 ++++----
hw/arm/pxa2xx_pic.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index f921a56..8123f05 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -334,10 +334,10 @@ static uint64_t pxa2xx_cpccnt_read(CPUARMState *env,
const ARMCPRegInfo *ri)
static const ARMCPRegInfo pxa_cp_reginfo[] = {
/* cp14 crm==1: perf registers */
{ .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
+ .access = PL1_RW, .type = ARM_CP_IO,
.readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
{ .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
+ .access = PL1_RW, .type = ARM_CP_IO,
.readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
{ .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -356,11 +356,11 @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
/* cp14 crn==6: CLKCFG */
{ .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
+ .access = PL1_RW, .type = ARM_CP_IO,
.readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
/* cp14 crn==7: PWRMODE */
{ .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
+ .access = PL1_RW, .type = ARM_CP_IO,
.readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
REGINFO_SENTINEL
};
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index 9cfc714..d41ac93 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -232,7 +232,7 @@ static void pxa2xx_pic_cp_write(CPUARMState *env, const
ARMCPRegInfo *ri,
#define REGINFO_FOR_PIC_CP(NAME, CRN) \
{ .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
- .access = PL1_RW, \
+ .access = PL1_RW, .type = ARM_CP_IO, \
.readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
--
1.9.1
- [Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address" for cpreg access exceptions, (continued)
- [Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address" for cpreg access exceptions, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 25/28] hw/arm/boot: fix rom_reset notifier registration order, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 24/28] arm: helper: rename get_phys_addr_mpu, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 22/28] arm: Implement uniprocessor with MP config, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 23/28] arm: Add has-mpu property, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 19/28] arm: Don't add v7mp registers in MPU systems, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 20/28] arm: helper: Factor out CP regs common to [pv]msa, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 18/28] arm: Do not define TLBTR in PMSA systems, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 16/28] hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 15/28] hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 12/28] hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO,
Peter Maydell <=
- [Qemu-devel] [PULL 08/28] target-arm: Fix REVIDR reset value, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 09/28] target-arm: add AArch32 MIDR aliases in ARMv8, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 05/28] target-arm/cpu.h: remove pending_exception, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 06/28] target-arm/kvm64: Add cortex-a53 cpu support, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 14/28] hw/arm/pxa2xx: Add reset method for pxa2xx_ssp, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 01/28] target-arm: Handle "extended small page" descriptors correctly, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 11/28] target-arm: Use the kernel's idea of MPIDR if we're using KVM, Peter Maydell, 2015/06/15
- [Qemu-devel] [PULL 10/28] MAINTAINERS: Add myself as ARM ACPI Subsystem maintainer, Peter Maydell, 2015/06/15