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[Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR |
Date: |
Thu, 24 Mar 2016 15:30:53 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
We should implement HW breakpoint/watchpoint, qemu supports them...
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a3c4fb1..29c4860 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1393,6 +1393,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
ifetch)
#define SPR_PSPB (0x09F)
#define SPR_DAWR (0x0B4)
#define SPR_RPR (0x0BA)
+#define SPR_CIABR (0x0BB)
#define SPR_DAWRX (0x0BC)
#define SPR_HFSCR (0x0BE)
#define SPR_VRSAVE (0x100)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bd62e3b..37c4fb5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7589,6 +7589,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DAWRX, 0x00000000);
+ spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_CIABR, 0x00000000);
}
static void gen_spr_970_dbg(CPUPPCState *env)
--
2.5.5
- [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 01/16] ppc64: set MSR_SF bit, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 04/16] ppc: Add macros to register hypervisor mode SPRs, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 14/16] hw/net/spapr_llan: Fix receive buffer handling for better performance, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 08/16] ppc: Initialize AMOR in PAPR mode, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR,
David Gibson <=
- [Qemu-devel] [PULL 15/16] hw/net/spapr_llan: Enable the RX buffer pools by default for new machines, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 02/16] spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 03/16] ppc: Update SPR definitions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 13/16] hw/net/spapr_llan: Extract rx buffer code into separate functions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 09/16] ppc: Fix writing to AMR/UAMOR, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 10/16] ppc: Add POWER8 IAMR register, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 16/16] ppc: move POWER8 Book4 regs in their own routine, David Gibson, 2016/03/24