[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper |
Date: |
Thu, 24 Mar 2016 15:30:48 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: removed LPCR setting ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr.c | 11 ++---------
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 23 ++++++++++++++++++++++-
3 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d43d6d9..ebbc6fe 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1613,15 +1613,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr,
PowerPCCPU *cpu,
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ);
- /* PAPR always has exception vectors in RAM not ROM. To ensure this,
- * MSR[IP] should never be set.
- */
- env->msr_mask &= ~(1 << 6);
-
- /* Tell KVM that we're in PAPR mode */
- if (kvm_enabled()) {
- kvmppc_set_papr(cpu);
- }
+ /* Enable PAPR mode in TCG or KVM */
+ cpu_ppc_set_papr(cpu);
if (cpu->max_compat) {
Error *local_err = NULL;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9ce301f..a7da0d3 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
+void cpu_ppc_set_papr(PowerPCCPU *cpu);
#endif
#endif
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3ecbd85..4d82e1c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8380,8 +8380,29 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
}
-#endif /* defined (TARGET_PPC64) */
+#if !defined(CONFIG_USER_ONLY)
+
+void cpu_ppc_set_papr(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ /* PAPR always has exception vectors in RAM not ROM. To ensure this,
+ * MSR[IP] should never be set.
+ *
+ * We also disallow setting of MSR_HV
+ */
+ env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
+
+ /* Tell KVM that we're in PAPR mode */
+ if (kvm_enabled()) {
+ kvmppc_set_papr(cpu);
+ }
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+#endif /* defined (TARGET_PPC64) */
/*****************************************************************************/
/* Generic CPU instantiation routine */
--
2.5.5
- [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 01/16] ppc64: set MSR_SF bit, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 04/16] ppc: Add macros to register hypervisor mode SPRs, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 14/16] hw/net/spapr_llan: Fix receive buffer handling for better performance, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 08/16] ppc: Initialize AMOR in PAPR mode, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 15/16] hw/net/spapr_llan: Enable the RX buffer pools by default for new machines, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper,
David Gibson <=
- [Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 02/16] spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 03/16] ppc: Update SPR definitions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 13/16] hw/net/spapr_llan: Extract rx buffer code into separate functions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 09/16] ppc: Fix writing to AMR/UAMOR, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 10/16] ppc: Add POWER8 IAMR register, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 16/16] ppc: move POWER8 Book4 regs in their own routine, David Gibson, 2016/03/24
- Re: [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324, Peter Maydell, 2016/03/24