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[Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8 |
Date: |
Thu, 24 Mar 2016 15:30:49 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
It's supposed to be an instruction counter. For now make us not
crash when accessing it.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a7da0d3..167c73f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1685,6 +1685,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
ifetch)
#define SPR_MPC_MD_DBRAM1 (0x32A)
#define SPR_RCPU_L2U_RA3 (0x32B)
#define SPR_TAR (0x32F)
+#define SPR_IC (0x350)
#define SPR_VTB (0x351)
#define SPR_MMCRC (0x353)
#define SPR_440_INV0 (0x370)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4d82e1c..3a13ad7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7924,6 +7924,17 @@ static void gen_spr_power8_pspb(CPUPPCState *env)
KVM_REG_PPC_PSPB, 0);
}
+static void gen_spr_power8_ic(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_IC, "IC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -7976,6 +7987,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int
version)
gen_spr_power8_tm(env);
gen_spr_power8_pspb(env);
gen_spr_vtb(env);
+ gen_spr_power8_ic(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);
--
2.5.5
- [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 01/16] ppc64: set MSR_SF bit, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 04/16] ppc: Add macros to register hypervisor mode SPRs, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 14/16] hw/net/spapr_llan: Fix receive buffer handling for better performance, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 08/16] ppc: Initialize AMOR in PAPR mode, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 15/16] hw/net/spapr_llan: Enable the RX buffer pools by default for new machines, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8,
David Gibson <=
- [Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 02/16] spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 03/16] ppc: Update SPR definitions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 13/16] hw/net/spapr_llan: Extract rx buffer code into separate functions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 09/16] ppc: Fix writing to AMR/UAMOR, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 10/16] ppc: Add POWER8 IAMR register, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 16/16] ppc: move POWER8 Book4 regs in their own routine, David Gibson, 2016/03/24
- Re: [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324, Peter Maydell, 2016/03/24