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[Qemu-devel] [RISU PATCH v3 14/18] x86.risu: add SSSE3 instructions
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From: |
Jan Bobek |
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Subject: |
[Qemu-devel] [RISU PATCH v3 14/18] x86.risu: add SSSE3 instructions |
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Date: |
Thu, 11 Jul 2019 18:32:56 -0400 |
Add SSSE3 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek <address@hidden>
---
x86.risu | 160 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/x86.risu b/x86.risu
index d40b9df..6f89a80 100644
--- a/x86.risu
+++ b/x86.risu
@@ -286,6 +286,36 @@ ADDSD SSE2 00001111 01011000 \
!constraints { repne($_); modrm($_); 1 } \
!memory { load(size => 8); }
+# NP 0F 38 01 /r: PHADDW mm1, mm2/m64
+PHADDW_mm SSSE3 00001111 00111000 00000001 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 01 /r: PHADDW xmm1, xmm2/m128
+PHADDW SSSE3 00001111 00111000 00000001 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 02 /r: PHADDD mm1, mm2/m64
+PHADDD_mm SSSE3 00001111 00111000 00000010 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 02 /r: PHADDD xmm1, xmm2/m128
+PHADDD SSSE3 00001111 00111000 00000010 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 03 /r: PHADDSW mm1, mm2/m64
+PHADDSW_mm SSSE3 00001111 00111000 00000011 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 03 /r: PHADDSW xmm1, xmm2/m128
+PHADDSW SSSE3 00001111 00111000 00000011 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
# F2 0F 7C /r: HADDPS xmm1, xmm2/m128
HADDPS SSE3 00001111 01111100 \
!constraints { repne($_); modrm($_); 1 } \
@@ -396,6 +426,36 @@ SUBSD SSE2 00001111 01011100 \
!constraints { repne($_); modrm($_); 1 } \
!memory { load(size => 8); }
+# NP 0F 38 05 /r: PHSUBW mm1, mm2/m64
+PHSUBW_mm SSSE3 00001111 00111000 00000101 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 05 /r: PHSUBW xmm1, xmm2/m128
+PHSUBW SSSE3 00001111 00111000 00000101 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 06 /r: PHSUBD mm1, mm2/m64
+PHSUBD_mm SSSE3 00001111 00111000 00000110 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 06 /r: PHSUBD xmm1, xmm2/m128
+PHSUBD SSSE3 00001111 00111000 00000110 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 07 /r: PHSUBSW mm1, mm2/m64
+PHSUBSW_mm SSSE3 00001111 00111000 00000111 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 07 /r: PHSUBSW xmm1, xmm2/m128
+PHSUBSW SSSE3 00001111 00111000 00000111 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
# F2 0F 7D /r: HSUBPS xmm1, xmm2/m128
HSUBPS SSE3 00001111 01111101 \
!constraints { repne($_); modrm($_); 1 } \
@@ -456,6 +516,16 @@ PMULUDQ SSE2 00001111 11110100 \
!constraints { data16($_); modrm($_); 1 } \
!memory { load(size => 16, align => 16); }
+# NP 0F 38 0B /r: PMULHRSW mm1, mm2/m64
+PMULHRSW_mm SSSE3 00001111 00111000 00001011 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 0B /r: PMULHRSW xmm1, xmm2/m128
+PMULHRSW SSSE3 00001111 00111000 00001011 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
# NP 0F 59 /r: MULPS xmm1, xmm2/m128
MULPS SSE 00001111 01011001 \
!constraints { modrm($_); 1 } \
@@ -486,6 +556,16 @@ PMADDWD SSE2 00001111 11110101 \
!constraints { data16($_); modrm($_); 1 } \
!memory { load(size => 16, align => 16); }
+# NP 0F 38 04 /r: PMADDUBSW mm1, mm2/m64
+PMADDUBSW_mm SSSE3 00001111 00111000 00000100 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 04 /r: PMADDUBSW xmm1, xmm2/m128
+PMADDUBSW SSSE3 00001111 00111000 00000100 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
# NP 0F 5E /r: DIVPS xmm1, xmm2/m128
DIVPS SSE 00001111 01011110 \
!constraints { modrm($_); 1 } \
@@ -656,6 +736,66 @@ PSADBW SSE2 00001111 11110110 \
!constraints { data16($_); modrm($_); 1 } \
!memory { load(size => 16, align => 16); }
+# NP 0F 38 1C /r: PABSB mm1, mm2/m64
+PABSB_mm SSSE3 00001111 00111000 00011100 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 1C /r: PABSB xmm1, xmm2/m128
+PABSB SSSE3 00001111 00111000 00011100 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 1D /r: PABSW mm1, mm2/m64
+PABSW_mm SSSE3 00001111 00111000 00011101 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 1D /r: PABSW xmm1, xmm2/m128
+PABSW SSSE3 00001111 00111000 00011101 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 1E /r: PABSD mm1, mm2/m64
+PABSD_mm SSSE3 00001111 00111000 00011110 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 1E /r: PABSD xmm1, xmm2/m128
+PABSD SSSE3 00001111 00111000 00011110 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 08 /r: PSIGNB mm1, mm2/m64
+PSIGNB_mm SSSE3 00001111 00111000 00001000 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 08 /r: PSIGNB xmm1, xmm2/m128
+PSIGNB SSSE3 00001111 00111000 00001000 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 09 /r: PSIGNW mm1, mm2/m64
+PSIGNW_mm SSSE3 00001111 00111000 00001001 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 09 /r: PSIGNW xmm1, xmm2/m128
+PSIGNW SSSE3 00001111 00111000 00001001 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
+# NP 0F 38 0A /r: PSIGND mm1, mm2/m64
+PSIGND_mm SSSE3 00001111 00111000 00001010 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 0A /r: PSIGND xmm1, xmm2/m128
+PSIGND SSSE3 00001111 00111000 00001010 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
#
# Comparison Instructions
# -----------------------
@@ -1003,6 +1143,16 @@ PSRAD_imm MMX 00001111 01110010 \
PSRAD_imm SSE2 00001111 01110010 \
!constraints { data16($_); modrm($_, reg => 4); imm($_, width => 8); defined
$_->{modrm}{reg2} }
+# NP 0F 3A 0F /r ib: PALIGNR mm1, mm2/m64, imm8
+PALIGNR_mm SSSE3 00001111 00111010 00001111 \
+ !constraints { modrm($_); imm($_, width => 8); $_->{modrm}{reg} &= 0b111;
$_->{modrm}{reg2} &= 0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 3A 0F /r ib: PALIGNR xmm1, xmm2/m128, imm8
+PALIGNR SSSE3 00001111 00111010 00001111 \
+ !constraints { data16($_); modrm($_); imm($_, width => 8); 1 } \
+ !memory { load(size => 16, align => 16); }
+
#
# Shuffle, Unpack, Blend, Insert, Extract, Broadcast, Permute, Gather
Instructions
#
--------------------------------------------------------------------------------
@@ -1128,6 +1278,16 @@ UNPCKHPD SSE2 00001111 00010101 \
!constraints { data16($_); modrm($_); 1 } \
!memory { load(size => 16, align => 16); }
+# NP 0F 38 00 /r: PSHUFB mm1, mm2/m64
+PSHUFB_mm SSSE3 00001111 00111000 00000000 \
+ !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
0b111 if defined $_->{modrm}{reg2}; 1 } \
+ !memory { load(size => 8); }
+
+# 66 0F 38 00 /r: PSHUFB xmm1, xmm2/m128
+PSHUFB SSSE3 00001111 00111000 00000000 \
+ !constraints { data16($_); modrm($_); 1 } \
+ !memory { load(size => 16, align => 16); }
+
# NP 0F 70 /r ib: PSHUFW mm1, mm2/m64, imm8
PSHUFW SSE 00001111 01110000 \
!constraints { modrm($_); imm($_, width => 8); $_->{modrm}{reg} &= 0b111;
$_->{modrm}{reg2} &= 0b111 if defined $_->{modrm}{reg2}; 1 } \
--
2.20.1
- [Qemu-devel] [RISU PATCH v3 04/18] risugen_x86_constraints: add module, (continued)
- [Qemu-devel] [RISU PATCH v3 04/18] risugen_x86_constraints: add module, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 15/18] x86.risu: add SSE4.1 and SSE4.2 instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 03/18] risugen_x86_asm: add module, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 14/18] x86.risu: add SSSE3 instructions,
Jan Bobek <=
- [Qemu-devel] [RISU PATCH v3 12/18] x86.risu: add SSE2 instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 17/18] x86.risu: add AVX instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 18/18] x86.risu: add AVX2 instructions, Jan Bobek, 2019/07/11