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Re: [Qemu-devel] [RISU PATCH v3 17/18] x86.risu: add AVX instructions
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [RISU PATCH v3 17/18] x86.risu: add AVX instructions |
Date: |
Sat, 20 Jul 2019 17:04:22 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 |
On 7/11/19 3:32 PM, Jan Bobek wrote:
> +# VEX.LIG.F3.0F.WIG 10 /r: VMOVSS xmm1, xmm2, xmm3
> +# VEX.LIG.F3.0F.WIG 10 /r: VMOVSS xmm1, m32
> +# VEX.LIG.F3.0F.WIG 11 /r: VMOVSS xmm1, xmm2, xmm3
> +# VEX.LIG.F3.0F.WIG 11 /r: VMOVSS m32, xmm1
> +VMOVSS AVX 0001000 d \
> + !constraints { vex($_, m => 0x0F, l => 0, p => 0xF3); modrm($_);
> $_->{vex}{v} = 0 unless defined $_->{modrm}{reg2}; 1 } \
> + !memory { $d ? store(size => 4) : load(size => 4); }
Why the l => 0? LIG does mean VEX.L ignored, so why not let it get randomized
as you do for WIG?
Not wrong as is... this is the documented value for scalar operands. But there
is a different document markup, LZ, for required (E)VEX.L == 0.
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [RISU PATCH v3 15/18] x86.risu: add SSE4.1 and SSE4.2 instructions, (continued)
- [Qemu-devel] [RISU PATCH v3 03/18] risugen_x86_asm: add module, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 14/18] x86.risu: add SSSE3 instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 12/18] x86.risu: add SSE2 instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 17/18] x86.risu: add AVX instructions, Jan Bobek, 2019/07/11
- Re: [Qemu-devel] [RISU PATCH v3 17/18] x86.risu: add AVX instructions,
Richard Henderson <=
- [Qemu-devel] [RISU PATCH v3 18/18] x86.risu: add AVX2 instructions, Jan Bobek, 2019/07/11
- Re: [Qemu-devel] [RISU PATCH v3 00/18] Support for generating x86 SIMD test images, Alex Bennée, 2019/07/12