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[PATCH 29/33] target/mips: Convert MSA MOVE.V opcode to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 29/33] target/mips: Convert MSA MOVE.V opcode to decodetree |
Date: |
Sat, 23 Oct 2021 23:47:59 +0200 |
Convert the MOVE.V opcode (Vector Move) to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 6 +++++-
target/mips/tcg/msa_translate.c | 26 +++++++++++++++++++++-----
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index dc5e561b9dc..1bde1983de3 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -23,6 +23,7 @@
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@elm_df ...... .... df:6 ws:5 wd:5 ...... &msa_elm
+@elm ...... .......... ws:5 wd:5 ...... &msa_elm df=0
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@@ -156,7 +157,10 @@ BNZ 010001 111 .. ..... ................
@bz
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
- COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
+ {
+ MOVE_V 011110 0010111110 ..... ..... 011001 @elm
+ COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
+ }
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ff5dbd99f84..b03cde964e0 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -31,7 +31,6 @@ enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -533,6 +532,26 @@ TRANS_DF_B(HADD_U, trans_msa_3r,
gen_helper_msa_hadd_u);
TRANS_DF_B(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s);
TRANS_DF_B(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u);
+static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
+{
+ TCGv_i32 tsr;
+ TCGv_i32 tdt;
+
+ if (!check_msa_access(ctx)) {
+ return false;
+ }
+
+ tsr = tcg_const_i32(a->ws);
+ tdt = tcg_const_i32(a->wd);
+
+ gen_helper_msa_move_v(cpu_env, tdt, tsr);
+
+ tcg_temp_free_i32(tdt);
+ tcg_temp_free_i32(tsr);
+
+ return true;
+}
+
static void gen_msa_elm_3e(DisasContext *ctx)
{
#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -551,9 +570,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
gen_store_gpr(telm, dest);
break;
- case OPC_MOVE_V:
- gen_helper_msa_move_v(cpu_env, tdt, tsr);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -665,7 +681,7 @@ static void gen_msa_elm(DisasContext *ctx)
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
if (dfn == 0x3E) {
- /* CTCMSA, CFCMSA, MOVE.V */
+ /* CTCMSA, CFCMSA */
gen_msa_elm_3e(ctx);
return;
}
--
2.31.1
- [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), (continued)
- [PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 27/33] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 29/33] target/mips: Convert MSA MOVE.V opcode to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 31/33] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 33/33] target/mips: Adjust style in msa_translate_init(), Philippe Mathieu-Daudé, 2021/10/23