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[PATCH v2 11/32] target/mips: Convert MSA SHF opcode to decodetree
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH v2 11/32] target/mips: Convert MSA SHF opcode to decodetree |
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Date: |
Wed, 27 Oct 2021 20:07:09 +0200 |
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- add &msa_i8 format
- !check_msa_enabled -> return true
- TCG timm is constant
---
target/mips/tcg/msa.decode | 4 ++++
target/mips/tcg/msa_translate.c | 37 ++++++++++++++++++---------------
2 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index c4699b9d4b7..7a4d7549258 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -16,6 +16,7 @@
&msa_bz df wt sa
&msa_ldi df wd sa
&msa_i5 df wd ws sa
+&msa_i8 df wd ws sa
&msa_bit df wd ws m
%dfm_df 16:7 !function=msa_bit_df
@@ -26,6 +27,7 @@
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
+@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit
df=%dfm_df m=%dfm_m
@@ -38,6 +40,8 @@ BZ 010001 110 .. ..... ................
@bz
BNZ 010001 111 .. ..... ................ @bz
{
+ SHF 011110 .. ........ ..... ..... 000010 @i8_df
+
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 175254c1e47..76c40dc7126 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -60,13 +60,10 @@ enum {
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
- OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
- OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
- OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
/* VEC/2R/2RF instruction */
@@ -477,20 +474,6 @@ static void gen_msa_i8(DisasContext *ctx)
case OPC_BSELI_B:
gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
break;
- case OPC_SHF_B:
- case OPC_SHF_H:
- case OPC_SHF_W:
- {
- uint8_t df = (ctx->opcode >> 24) & 0x3;
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- } else {
- TCGv_i32 tdf = tcg_const_i32(df);
- gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
- tcg_temp_free_i32(tdf);
- }
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -502,6 +485,26 @@ static void gen_msa_i8(DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
+static bool trans_SHF(DisasContext *ctx, arg_msa_i8 *a)
+{
+ if (a->df == DF_DOUBLE) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_helper_msa_shf_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->sa));
+
+ return true;
+}
+
static bool trans_msa_i5(DisasContext *ctx, arg_msa_i5 *a,
gen_helper_piiii *gen_msa_i5)
{
--
2.31.1
- Re: [PATCH v2 04/32] target/mips: Use dup_const() to simplify, (continued)
- [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 10/32] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 11/32] target/mips: Convert MSA SHF opcode to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 13/32] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 14/32] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 15/32] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27