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[PATCH v2 05/20] disas/nanomips: Remove __cond methods from class
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From: |
Milica Lazarevic |
|
Subject: |
[PATCH v2 05/20] disas/nanomips: Remove __cond methods from class |
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Date: |
Mon, 5 Sep 2022 11:55:07 +0200 |
NMD class methods with the conditional_function type like
NMD::ADDIU_32__cond, NMD::ADDIU_RS5__cond, etc. are removed from the NMD
class. They're now declared global static functions. Therefore, typedef
of the function pointer, conditional_function is defined outside of the
class.
Now that conditional_function type functions are not part of the NMD
class we can't access them using the this pointer. Thus, the use of
the this pointer has been deleted.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
disas/nanomips.cpp | 42 +++++++++++++++++++++---------------------
disas/nanomips.h | 14 ++------------
2 files changed, 23 insertions(+), 33 deletions(-)
diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
index 91ea35bf75..ecc3e7efda 100644
--- a/disas/nanomips.cpp
+++ b/disas/nanomips.cpp
@@ -781,7 +781,7 @@ int NMD::Disassemble(const uint16 * data, std::string & dis,
if ((op_code & table[i].mask) == table[i].value) {
/* possible match */
conditional_function cond = table[i].condition;
- if ((cond == 0) || (this->*cond)(op_code)) {
+ if ((cond == NULL) || cond(op_code)) {
try
{
if (table[i].type == pool) {
@@ -1678,28 +1678,28 @@ static uint64 extract_u_3_2_1_0__s1(uint64 instruction)
-bool NMD::ADDIU_32__cond(uint64 instruction)
+static bool ADDIU_32__cond(uint64 instruction)
{
uint64 rt = extract_rt_25_24_23_22_21(instruction);
return rt != 0;
}
-bool NMD::ADDIU_RS5__cond(uint64 instruction)
+static bool ADDIU_RS5__cond(uint64 instruction)
{
uint64 rt = extract_rt_9_8_7_6_5(instruction);
return rt != 0;
}
-bool NMD::BALRSC_cond(uint64 instruction)
+static bool BALRSC_cond(uint64 instruction)
{
uint64 rt = extract_rt_25_24_23_22_21(instruction);
return rt != 0;
}
-bool NMD::BEQC_16__cond(uint64 instruction)
+static bool BEQC_16__cond(uint64 instruction)
{
uint64 rs3 = extract_rs3_6_5_4(instruction);
uint64 rt3 = extract_rt3_9_8_7(instruction);
@@ -1708,7 +1708,7 @@ bool NMD::BEQC_16__cond(uint64 instruction)
}
-bool NMD::BNEC_16__cond(uint64 instruction)
+static bool BNEC_16__cond(uint64 instruction)
{
uint64 rs3 = extract_rs3_6_5_4(instruction);
uint64 rt3 = extract_rt3_9_8_7(instruction);
@@ -1717,35 +1717,35 @@ bool NMD::BNEC_16__cond(uint64 instruction)
}
-bool NMD::MOVE_cond(uint64 instruction)
+static bool MOVE_cond(uint64 instruction)
{
uint64 rt = extract_rt_9_8_7_6_5(instruction);
return rt != 0;
}
-bool NMD::P16_BR1_cond(uint64 instruction)
+static bool P16_BR1_cond(uint64 instruction)
{
uint64 u = extract_u_3_2_1_0__s1(instruction);
return u != 0;
}
-bool NMD::PREF_S9__cond(uint64 instruction)
+static bool PREF_S9__cond(uint64 instruction)
{
uint64 hint = extract_hint_25_24_23_22_21(instruction);
return hint != 31;
}
-bool NMD::PREFE_cond(uint64 instruction)
+static bool PREFE_cond(uint64 instruction)
{
uint64 hint = extract_hint_25_24_23_22_21(instruction);
return hint != 31;
}
-bool NMD::SLTU_cond(uint64 instruction)
+static bool SLTU_cond(uint64 instruction)
{
uint64 rd = extract_rd_15_14_13_12_11(instruction);
return rd != 0;
@@ -16698,7 +16698,7 @@ NMD::Pool NMD::P_ADDIU[2] = {
0xffe00000, 0x00000000, 0 , 0,
0x0 }, /* P.RI */
{ instruction , 0 , 0 , 32,
- 0xfc000000, 0x00000000, &NMD::ADDIU_32_ , &NMD::ADDIU_32__cond
,
+ 0xfc000000, 0x00000000, &NMD::ADDIU_32_ , &ADDIU_32__cond ,
0x0 }, /* ADDIU[32] */
};
@@ -16796,7 +16796,7 @@ NMD::Pool NMD::P_SLTU[2] = {
0xfc00fbff, 0x20000390, 0 , 0,
0x0 }, /* P.DVP */
{ instruction , 0 , 0 , 32,
- 0xfc0003ff, 0x20000390, &NMD::SLTU , &NMD::SLTU_cond
,
+ 0xfc0003ff, 0x20000390, &NMD::SLTU , &SLTU_cond ,
0x0 }, /* SLTU */
};
@@ -21341,7 +21341,7 @@ NMD::Pool NMD::P_PREF_S9_[2] = {
0xffe07f00, 0xa7e01800, &NMD::SYNCI , 0,
0x0 }, /* SYNCI */
{ instruction , 0 , 0 , 32,
- 0xfc007f00, 0xa4001800, &NMD::PREF_S9_ , &NMD::PREF_S9__cond
,
+ 0xfc007f00, 0xa4001800, &NMD::PREF_S9_ , &PREF_S9__cond ,
0x0 }, /* PREF[S9] */
};
@@ -21553,7 +21553,7 @@ NMD::Pool NMD::P_PREFE[2] = {
0xffe07f00, 0xa7e01a00, &NMD::SYNCIE , 0,
CP0_ | EVA_ }, /* SYNCIE */
{ instruction , 0 , 0 , 32,
- 0xfc007f00, 0xa4001a00, &NMD::PREFE , &NMD::PREFE_cond
,
+ 0xfc007f00, 0xa4001a00, &NMD::PREFE , &PREFE_cond ,
CP0_ | EVA_ }, /* PREFE */
};
@@ -21725,7 +21725,7 @@ NMD::Pool NMD::P_BALRSC[2] = {
0xffe0f000, 0x48008000, &NMD::BRSC , 0,
0x0 }, /* BRSC */
{ call_instruction , 0 , 0 , 32,
- 0xfc00f000, 0x48008000, &NMD::BALRSC , &NMD::BALRSC_cond
,
+ 0xfc00f000, 0x48008000, &NMD::BALRSC , &BALRSC_cond ,
0x0 }, /* BALRSC */
};
@@ -22073,7 +22073,7 @@ NMD::Pool NMD::P16_MV[2] = {
0xffe0 , 0x1000 , 0 , 0,
0x0 }, /* P16.RI */
{ instruction , 0 , 0 , 16,
- 0xfc00 , 0x1000 , &NMD::MOVE , &NMD::MOVE_cond
,
+ 0xfc00 , 0x1000 , &NMD::MOVE , &MOVE_cond ,
0x0 }, /* MOVE */
};
@@ -22139,7 +22139,7 @@ NMD::Pool NMD::P_ADDIU_RS5_[2] = {
0xffe8 , 0x9008 , &NMD::NOP_16_ , 0,
0x0 }, /* NOP[16] */
{ instruction , 0 , 0 , 16,
- 0xfc08 , 0x9008 , &NMD::ADDIU_RS5_ , &NMD::ADDIU_RS5__cond
,
+ 0xfc08 , 0x9008 , &NMD::ADDIU_RS5_ , &ADDIU_RS5__cond ,
0x0 }, /* ADDIU[RS5] */
};
@@ -22176,10 +22176,10 @@ NMD::Pool NMD::P16_JRC[2] = {
NMD::Pool NMD::P16_BR1[2] = {
{ branch_instruction , 0 , 0 , 16,
- 0xfc00 , 0xd800 , &NMD::BEQC_16_ , &NMD::BEQC_16__cond
,
+ 0xfc00 , 0xd800 , &NMD::BEQC_16_ , &BEQC_16__cond ,
XMMS_ }, /* BEQC[16] */
{ branch_instruction , 0 , 0 , 16,
- 0xfc00 , 0xd800 , &NMD::BNEC_16_ , &NMD::BNEC_16__cond
,
+ 0xfc00 , 0xd800 , &NMD::BNEC_16_ , &BNEC_16__cond ,
XMMS_ }, /* BNEC[16] */
};
@@ -22189,7 +22189,7 @@ NMD::Pool NMD::P16_BR[2] = {
0xfc0f , 0xd800 , 0 , 0,
0x0 }, /* P16.JRC */
{ pool , P16_BR1 , 2 , 16,
- 0xfc00 , 0xd800 , 0 , &NMD::P16_BR1_cond
,
+ 0xfc00 , 0xd800 , 0 , &P16_BR1_cond ,
0x0 }, /* P16.BR1 */
};
diff --git a/disas/nanomips.h b/disas/nanomips.h
index c8a098922c..ff91fbf8c6 100644
--- a/disas/nanomips.h
+++ b/disas/nanomips.h
@@ -31,6 +31,8 @@ typedef uint32_t uint32;
typedef uint16_t uint16;
typedef uint64_t img_address;
+typedef bool (*conditional_function)(uint64 instruction);
+
enum TABLE_ENTRY_TYPE {
instruction,
call_instruction,
@@ -72,7 +74,6 @@ private:
typedef std::string(NMD:: *disassembly_function)(uint64 instruction,
img_address m_pc);
- typedef bool(NMD:: *conditional_function)(uint64 instruction);
struct Pool {
TABLE_ENTRY_TYPE type;
@@ -91,17 +92,6 @@ private:
TABLE_ENTRY_TYPE & type, const Pool *table,
int table_size, img_address m_pc);
- bool ADDIU_32__cond(uint64 instruction);
- bool ADDIU_RS5__cond(uint64 instruction);
- bool BALRSC_cond(uint64 instruction);
- bool BEQC_16__cond(uint64 instruction);
- bool BNEC_16__cond(uint64 instruction);
- bool MOVE_cond(uint64 instruction);
- bool P16_BR1_cond(uint64 instruction);
- bool PREF_S9__cond(uint64 instruction);
- bool PREFE_cond(uint64 instruction);
- bool SLTU_cond(uint64 instruction);
-
std::string ABS_D(uint64 instruction, img_address m_pc);
std::string ABS_S(uint64 instruction, img_address m_pc);
std::string ABSQ_S_PH(uint64 instruction, img_address m_pc);
--
2.25.1
- [PATCH v2 0/20] Convert nanoMIPS disassembler from C++ to C, Milica Lazarevic, 2022/09/05
- [PATCH v2 01/20] disas/nanomips: Remove namespace img, Milica Lazarevic, 2022/09/05
- [PATCH v2 02/20] disas/nanomips: Extract enums out of the NMD class, Milica Lazarevic, 2022/09/05
- [PATCH v2 05/20] disas/nanomips: Remove __cond methods from class,
Milica Lazarevic <=
- [PATCH v2 03/20] disas/nanomips: Delete NMD class fields, Milica Lazarevic, 2022/09/05
- [PATCH v2 04/20] disas/nanomips: Remove helper methods from class, Milica Lazarevic, 2022/09/05
- [PATCH v2 06/20] disas/nanomips: Remove disasm methods from class, Milica Lazarevic, 2022/09/05
- [PATCH v2 07/20] disas/nanomips: Remove Pool tables from the class, Milica Lazarevic, 2022/09/05