Re: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs

[Peter Maydell]

On Mon, 26 Sept 2022 at 15:13, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> We currently have hacks across the hw/ to reference current_cpu to
> work out what the current accessing CPU is. This breaks in some cases
> including using gdbstub to access HW state. As we have MemTxAttrs to
> describe details about the access lets extend it to mention if this is
> a CPU access and which one it is.
>
> There are a number of places we need to fix up including:
>
>   CPU helpers directly calling address_space_*() fns
>   models in hw/ fishing the data out of current_cpu
>   hypervisors offloading device emulation to QEMU
>
> I'll start addressing some of these in following patches.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>
> ---
> v2
>   - use separate field cpu_index
>   - bool for requester_is_cpu
> v3
>   - switch to enum MemTxRequesterType
>   - move helper #define to patch
>   - revert to overloading requester_id
>   - mention hypervisors in commit message
>   - drop cputlb tweaks, they will move to target specific code

I still don't see anything in this patchset that updates
the code which currently assumes requester_id to be a PCI
index to check that it hasn't been handed a MemTxAttrs
that uses requester_id as a CPU number.

I also still need to go and look up how hardware does this,
so please don't queue this patchset yet. In particular, we
should think about whether we want this to be:
 * a CPU number, but only set opt-in by some target archs
 * a CPU number, valid for all target archs
 * a unique-within-the-machine identifier of the transaction
   master (i.e. which can be set by DMA controllers, etc,
   not just CPUs)

I would also like some input from Edgar since I know Xilinx
have some more extensive out-of-tree uses of requester_id.
We aren't obligated to not break out-of-tree code, but that
seems like a bunch of experience and knowledge about how
real hardware works that would be useful for informing
how we design this.

thanks
-- PMM