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Re: [PATCH v2 02/11] target/arm: enable tracking of CPU index in MemTxAt
From: |
Peter Maydell |
Subject: |
Re: [PATCH v2 02/11] target/arm: enable tracking of CPU index in MemTxAttrs |
Date: |
Mon, 26 Sep 2022 16:07:45 +0100 |
On Mon, 26 Sept 2022 at 16:06, Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
> > On Mon, 26 Sept 2022 at 14:39, Alex Bennée <alex.bennee@linaro.org> wrote:
> > This only catches the case where the memory access is
> > done via something that does a virtual-to-physical translation.
> > It misses memory accesses done directly on physical addresses,
> > such as those in arm_ldl_ptw() and arm_ldq_ptw(), plus various
> > M-profile specific ones.
>
> I thought they were just used for the page table walk. Can you place
> your page tables aliases with a piece of HW?
They are just used for the page table walk, but they are
nonetheless still memory transactions initiated by the CPU,
so if we're saying those should be marked up in the
transaction-attributes struct then they should count.
thanks
-- PMM
- [PATCH v2 00/11] gdbstub/next (MemTxAttrs and re-factoring), Alex Bennée, 2022/09/26
- [PATCH v2 07/11] configure: move detected gdb to TCG's config-host.mak, Alex Bennée, 2022/09/26
- [PATCH v2 04/11] qtest: make read/write operation appear to be from CPU, Alex Bennée, 2022/09/26
- [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs, Alex Bennée, 2022/09/26
- Re: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs, Alexander Graf, 2022/09/26
[PATCH v2 03/11] target/arm: ensure HVF traps set appropriate MemTxAttrs, Alex Bennée, 2022/09/26