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Re: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs |
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Date: |
Mon, 26 Sep 2022 16:30:48 +0100 |
On Mon, 26 Sept 2022 at 16:24, Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Peter Maydell <peter.maydell@linaro.org> writes:
> > I still don't see anything in this patchset that updates
> > the code which currently assumes requester_id to be a PCI
> > index to check that it hasn't been handed a MemTxAttrs
> > that uses requester_id as a CPU number.
>
> OK I'll update so all the existing cases setting requester_id also set
> the type to MEMTXATTRS_MSI.
The problem is not the places that set requester_id (you can
arrange for the default to be MSI for back-compat if you don't
want to explicitly set it), but the places that *read* it.
-- PMM
- [PATCH v2 00/11] gdbstub/next (MemTxAttrs and re-factoring), Alex Bennée, 2022/09/26
- [PATCH v2 07/11] configure: move detected gdb to TCG's config-host.mak, Alex Bennée, 2022/09/26
- [PATCH v2 04/11] qtest: make read/write operation appear to be from CPU, Alex Bennée, 2022/09/26
- [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs, Alex Bennée, 2022/09/26
- Re: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs, Alexander Graf, 2022/09/26
[PATCH v2 03/11] target/arm: ensure HVF traps set appropriate MemTxAttrs, Alex Bennée, 2022/09/26
[PATCH v2 08/11] gdbstub: move into its own sub directory, Alex Bennée, 2022/09/26
[PATCH v2 06/11] hw/timer: convert mptimer access to attrs to derive cpu index, Alex Bennée, 2022/09/26
[PATCH v2 09/11] gdbstub: move sstep flags probing into AccelClass, Alex Bennée, 2022/09/26
[PATCH v2 10/11] gdbstub: move breakpoint logic to accel ops, Alex Bennée, 2022/09/26
[PATCH v2 05/11] hw/intc/gic: use MxTxAttrs to divine accessing CPU, Alex Bennée, 2022/09/26