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[PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC proper
From: |
Alistair Francis |
Subject: |
[PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property |
Date: |
Tue, 27 Sep 2022 16:30:52 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
QEMU we don't run the ROM code and instead just jump to the next stage.
This means we need to be a little more flexible about what the resetvec
is.
This patch allows us to set the resetvec from the command line with
something like this:
-global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400
This way as the next stage changes we can update the resetvec.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 8 +++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 26d960f288..6665cd5794 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -46,6 +46,8 @@ struct LowRISCIbexSoCState {
IbexTimerState timer;
IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
+ uint32_t resetvec;
+
MemoryRegion flash_mem;
MemoryRegion rom;
MemoryRegion flash_alias;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 45c92c9bbc..be7ff1eea0 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
@@ -297,10 +297,16 @@ static void lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
}
+static Property lowrisc_ibex_soc_props[] = {
+ DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, lowrisc_ibex_soc_props);
dc->realize = lowrisc_ibex_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
--
2.37.3
- [PULL v2 00/22] riscv-to-apply queue, Alistair Francis, 2022/09/27
- [PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host, Alistair Francis, 2022/09/27
- [PULL v2 02/22] hw/ssi: ibex_spi: update reg addr, Alistair Francis, 2022/09/27
- [PULL v2 03/22] docs/system: clean up code escape for riscv virt platform, Alistair Francis, 2022/09/27
- [PULL v2 04/22] target/riscv: Remove sideleg and sedeleg, Alistair Francis, 2022/09/27
- [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/27
- [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/27
- [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/27
- [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}, Alistair Francis, 2022/09/27
- [PULL v2 08/22] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/27
- [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property,
Alistair Francis <=
- [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/27
- [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Alistair Francis, 2022/09/27
- [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type, Alistair Francis, 2022/09/27
- [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, Alistair Francis, 2022/09/27
- [PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger, Alistair Francis, 2022/09/27
- [PULL v2 18/22] target/riscv: debug: Create common trigger actions function, Alistair Francis, 2022/09/27
- [PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written, Alistair Francis, 2022/09/27
- [PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code, Alistair Francis, 2022/09/27
- [PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR, Alistair Francis, 2022/09/27
- [PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered, Alistair Francis, 2022/09/27