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[PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_
From: |
Alistair Francis |
Subject: |
[PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() |
Date: |
Wed, 14 Jun 2023 11:19:28 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 89a1a25812..9f2c8fa7c6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1294,13 +1294,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
-
-#ifndef CONFIG_USER_ONLY
- if (cpu->cfg.ext_sstc) {
- riscv_timer_init(cpu);
- }
-#endif /* CONFIG_USER_ONLY */
-
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -1308,6 +1301,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
#ifndef CONFIG_USER_ONLY
+ if (cpu->cfg.ext_sstc) {
+ riscv_timer_init(cpu);
+ }
+
if (cpu->cfg.pmu_num) {
if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
--
2.40.1
- [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero, (continued)
- [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero, Alistair Francis, 2023/06/13
- [PULL 02/60] target/riscv: Move zc* out of the experimental properties, Alistair Francis, 2023/06/13
- [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v(), Alistair Francis, 2023/06/13
- [PULL 04/60] target/riscv/cpu.c: remove set_vext_version(), Alistair Francis, 2023/06/13
- [PULL 05/60] target/riscv/cpu.c: remove set_priv_version(), Alistair Francis, 2023/06/13
- [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST, Alistair Francis, 2023/06/13
- [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version, Alistair Francis, 2023/06/13
- [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd, Alistair Francis, 2023/06/13
- [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers, Alistair Francis, 2023/06/13
- [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl(), Alistair Francis, 2023/06/13
- [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init(),
Alistair Francis <=
- [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Alistair Francis, 2023/06/13
- [PULL 13/60] target/riscv: rework write_misa(), Alistair Francis, 2023/06/13
- [PULL 14/60] target/riscv: Update pmp_get_tlb_size(), Alistair Francis, 2023/06/13
- [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Alistair Francis, 2023/06/13
- [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs, Alistair Francis, 2023/06/13
- [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed, Alistair Francis, 2023/06/13
- [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Alistair Francis, 2023/06/13
- [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Alistair Francis, 2023/06/13
- [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Alistair Francis, 2023/06/13
- [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Alistair Francis, 2023/06/13