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[PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs
From: |
Alistair Francis |
Subject: |
[PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() |
Date: |
Wed, 14 Jun 2023 11:19:36 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
The addr and size parameters in pmp_hart_has_privs_default() are unused.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9a6e04cda0..2403039133 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -236,8 +236,7 @@ static int pmp_is_in_range(CPURISCVState *env, int
pmp_index,
/*
* Check if the address has required RWX privs when no PMP entry is matched.
*/
-static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
- target_ulong size, pmp_priv_t privs,
+static bool pmp_hart_has_privs_default(CPURISCVState *env, pmp_priv_t privs,
pmp_priv_t *allowed_privs,
target_ulong mode)
{
@@ -309,8 +308,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
- return pmp_hart_has_privs_default(env, addr, size, privs,
- allowed_privs, mode);
+ return pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
}
if (size == 0) {
@@ -454,8 +452,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
/* No rule matched */
if (!ret) {
- ret = pmp_hart_has_privs_default(env, addr, size, privs,
- allowed_privs, mode);
+ ret = pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
}
return ret;
--
2.40.1
- [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init(), (continued)
- [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init(), Alistair Francis, 2023/06/13
- [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Alistair Francis, 2023/06/13
- [PULL 13/60] target/riscv: rework write_misa(), Alistair Francis, 2023/06/13
- [PULL 14/60] target/riscv: Update pmp_get_tlb_size(), Alistair Francis, 2023/06/13
- [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Alistair Francis, 2023/06/13
- [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs, Alistair Francis, 2023/06/13
- [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed, Alistair Francis, 2023/06/13
- [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Alistair Francis, 2023/06/13
- [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Alistair Francis, 2023/06/13
- [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Alistair Francis, 2023/06/13
- [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(),
Alistair Francis <=
- [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated, Alistair Francis, 2023/06/13
- [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Alistair Francis, 2023/06/13
- [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Alistair Francis, 2023/06/13
- [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry, Alistair Francis, 2023/06/13
- [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions, Alistair Francis, 2023/06/13
- [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro, Alistair Francis, 2023/06/13
- [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition, Alistair Francis, 2023/06/13
- [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition, Alistair Francis, 2023/06/13
- [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size, Alistair Francis, 2023/06/13
- [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs, Alistair Francis, 2023/06/13