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[PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions
From: |
Alistair Francis |
Subject: |
[PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions |
Date: |
Wed, 14 Jun 2023 11:19:43 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Follow QOM style which declares FOO_init() as instance
initializer and FOO_class_init() as class initializer:
rename the OpenTitan machine class/instance init()
accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index bc678766e7..2d21ee39c5 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -75,7 +75,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
-static void opentitan_board_init(MachineState *machine)
+static void opentitan_machine_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const MemMapEntry *memmap = ibex_memmap;
@@ -108,17 +108,17 @@ static void opentitan_board_init(MachineState *machine)
}
}
-static void opentitan_machine_init(MachineClass *mc)
+static void opentitan_machine_class_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with OpenTitan";
- mc->init = opentitan_board_init;
+ mc->init = opentitan_machine_init;
mc->max_cpus = 1;
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
mc->default_ram_id = "riscv.lowrisc.ibex.ram";
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
-DEFINE_MACHINE("opentitan", opentitan_machine_init)
+DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
static void lowrisc_ibex_soc_init(Object *obj)
{
--
2.40.1
- [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs, (continued)
- [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs, Alistair Francis, 2023/06/13
- [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed, Alistair Francis, 2023/06/13
- [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Alistair Francis, 2023/06/13
- [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Alistair Francis, 2023/06/13
- [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Alistair Francis, 2023/06/13
- [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Alistair Francis, 2023/06/13
- [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated, Alistair Francis, 2023/06/13
- [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Alistair Francis, 2023/06/13
- [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Alistair Francis, 2023/06/13
- [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry, Alistair Francis, 2023/06/13
- [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions,
Alistair Francis <=
- [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro, Alistair Francis, 2023/06/13
- [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition, Alistair Francis, 2023/06/13
- [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition, Alistair Francis, 2023/06/13
- [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size, Alistair Francis, 2023/06/13
- [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs, Alistair Francis, 2023/06/13
- [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address, Alistair Francis, 2023/06/13
- [PULL 34/60] target/riscv: smstateen check for fcsr, Alistair Francis, 2023/06/13
- [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info, Alistair Francis, 2023/06/13
- [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes, Alistair Francis, 2023/06/13
- [PULL 36/60] target/riscv: smstateen knobs, Alistair Francis, 2023/06/13