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[PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disasse
From: |
Alistair Francis |
Subject: |
[PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info |
Date: |
Wed, 14 Jun 2023 11:19:56 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 10 +++++++---
target/riscv/cpu.c | 1 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index d597161d46..f2dd5fd531 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "disas/dis-asm.h"
-
+#include "target/riscv/cpu_cfg.h"
/* types */
@@ -969,6 +969,7 @@ typedef enum {
/* structures */
typedef struct {
+ RISCVCPUConfig *cfg;
uint64_t pc;
uint64_t inst;
int32_t imm;
@@ -4861,11 +4862,13 @@ static void decode_inst_decompress(rv_decode *dec,
rv_isa isa)
/* disassemble instruction */
static void
-disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
+disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
+ RISCVCPUConfig *cfg)
{
rv_decode dec = { 0 };
dec.pc = pc;
dec.inst = inst;
+ dec.cfg = cfg;
decode_inst_opcode(&dec, isa);
decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa);
@@ -4920,7 +4923,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info
*info, rv_isa isa)
break;
}
- disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
+ disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
+ (RISCVCPUConfig *)info->target_info);
(*info->fprintf_func)(info->stream, "%s", buf);
return len;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d23b4c4d16..938c7bd87b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -849,6 +849,7 @@ static void riscv_cpu_reset_hold(Object *obj)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
RISCVCPU *cpu = RISCV_CPU(s);
+ info->target_info = &cpu->cfg;
switch (riscv_cpu_mxl(&cpu->env)) {
case MXL_RV32:
--
2.40.1
- [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, (continued)
- [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Alistair Francis, 2023/06/13
- [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry, Alistair Francis, 2023/06/13
- [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions, Alistair Francis, 2023/06/13
- [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro, Alistair Francis, 2023/06/13
- [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition, Alistair Francis, 2023/06/13
- [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition, Alistair Francis, 2023/06/13
- [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size, Alistair Francis, 2023/06/13
- [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs, Alistair Francis, 2023/06/13
- [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address, Alistair Francis, 2023/06/13
- [PULL 34/60] target/riscv: smstateen check for fcsr, Alistair Francis, 2023/06/13
- [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info,
Alistair Francis <=
- [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes, Alistair Francis, 2023/06/13
- [PULL 36/60] target/riscv: smstateen knobs, Alistair Francis, 2023/06/13
- [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer, Alistair Francis, 2023/06/13
- [PULL 35/60] target/riscv: Reuse tb->flags.FS, Alistair Francis, 2023/06/13
- [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h, Alistair Francis, 2023/06/13
- [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions, Alistair Francis, 2023/06/13
- [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters, Alistair Francis, 2023/06/13
- [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions, Alistair Francis, 2023/06/13
- [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions, Alistair Francis, 2023/06/13
- [PULL 45/60] target/riscv: Fix target address to update badaddr, Alistair Francis, 2023/06/13