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[PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions
From: |
Alistair Francis |
Subject: |
[PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions |
Date: |
Wed, 14 Jun 2023 11:19:58 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 6659f92179..c9a81af662 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4598,16 +4598,24 @@ static void format_inst(char *buf, size_t buflen,
size_t tab, rv_decode *dec)
append(buf, rv_ireg_name_sym[dec->rs2], buflen);
break;
case '3':
- append(buf, rv_freg_name_sym[dec->rd], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] :
+ rv_freg_name_sym[dec->rd],
+ buflen);
break;
case '4':
- append(buf, rv_freg_name_sym[dec->rs1], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] :
+ rv_freg_name_sym[dec->rs1],
+ buflen);
break;
case '5':
- append(buf, rv_freg_name_sym[dec->rs2], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] :
+ rv_freg_name_sym[dec->rs2],
+ buflen);
break;
case '6':
- append(buf, rv_freg_name_sym[dec->rs3], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] :
+ rv_freg_name_sym[dec->rs3],
+ buflen);
break;
case '7':
snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
--
2.40.1
- [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address, (continued)
- [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address, Alistair Francis, 2023/06/13
- [PULL 34/60] target/riscv: smstateen check for fcsr, Alistair Francis, 2023/06/13
- [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info, Alistair Francis, 2023/06/13
- [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes, Alistair Francis, 2023/06/13
- [PULL 36/60] target/riscv: smstateen knobs, Alistair Francis, 2023/06/13
- [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer, Alistair Francis, 2023/06/13
- [PULL 35/60] target/riscv: Reuse tb->flags.FS, Alistair Francis, 2023/06/13
- [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h, Alistair Francis, 2023/06/13
- [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions, Alistair Francis, 2023/06/13
- [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters, Alistair Francis, 2023/06/13
- [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions,
Alistair Francis <=
- [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions, Alistair Francis, 2023/06/13
- [PULL 45/60] target/riscv: Fix target address to update badaddr, Alistair Francis, 2023/06/13
- [PULL 44/60] disas/riscv.c: Remove redundant parentheses, Alistair Francis, 2023/06/13
- [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext, Alistair Francis, 2023/06/13
- [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements, Alistair Francis, 2023/06/13
- [PULL 50/60] target/riscv: Enable PC-relative translation, Alistair Francis, 2023/06/13
- [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none", Alistair Francis, 2023/06/13
- [PULL 53/60] riscv/virt: Support using pflash via -blockdev option, Alistair Francis, 2023/06/13
- [PULL 55/60] util/log: Add vector registers to log, Alistair Francis, 2023/06/13
- [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask, Alistair Francis, 2023/06/13